OXCFU950 DATA SHEET
OXFORD SEMICONDUCTOR, INC.
8.11.3
8.11.4
8.11.5
8.11.6
8.11.7
8.11.8
8.11.9
ADDITIONAL CONTROL REGISTER—ACR................................................................................................................ 57
TRANSMITTER TRIGGER LEVEL—TTL ..................................................................................................................... 58
RECEIVER INTERRUPT. TRIGGER LEVEL—RTL ..................................................................................................... 59
FLOW CONTROL LEVELS—FCL & FCH..................................................................................................................... 59
DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 59
NINE-BIT MODE REGISTER—NMR............................................................................................................................ 59
MODEM DISABLE MASK—MDM................................................................................................................................. 60
8.11.10 READABLE FICR—RFC............................................................................................................................................... 60
8.11.11 GOOD-DATA STATUS REGISTER—GDS................................................................................................................... 61
8.11.12 DMA STATUS REGISTER—DMS ................................................................................................................................ 61
8.11.13 PORT INDEX REGISTER—PIX.................................................................................................................................... 61
8.11.14 ALTERNATIVE UART BAUD RATE CONTROL REGISTERS: A_LATCH, A_ENABLE, A_DLL, A_DLM, A_CPR,
A_TCR 61
8.11.15 ALTERNATIVE 32-BIT FIFO ACCESS ENABLE: DBURST ..................................................................................... 61
9
MULTI PURPOSE I/O (MIO) AND USB POWER MANAGEMENT MODULE.....................................62
INTERNAL EEPROM SPECIFICATION...........................................................................................62
10
10.1 ZONE 0 : ZONE HEADER ................................................................................................................................................ 63
10.2 ZONE 1 : CIS CONFIGURATION ZONE .......................................................................................................................... 63
10.3 ZONE 2 : USB FUNCTION ACCESS ZONE. ................................................................................................................... 64
10.4 ZONE 3 : UART FUNCTION ACCESS............................................................................................................................. 64
11
12
13
INTRODUCTION TO THE OXCFU950 SOFTWARE DRIVERS.......................................................65
OPERATING CONDITIONS.............................................................................................................66
DC ELECTRICAL CHARACTERISTICS..........................................................................................67
13.1 2.85 V TO 3.6 V OPERATION........................................................................................................................................... 67
14
TIMING WAVEFORMS / AC CHARACTERISTICS .........................................................................68
14.1 MEMORY ACCESS........................................................................................................................................................... 68
14.2 I/O ACCESS...................................................................................................................................................................... 69
15
PACKAGE INFORMATION..............................................................................................................71
15.1 PACKAGE DIMENSIONS................................................................................................................................................. 72
16
ORDERING INFORMATION ............................................................................................................72
NOTES ........................................................................................................................................................73
CONTACT DETAILS...................................................................................................................................74
DISCLAIMER ..............................................................................................................................................74
REVISION HISTORY
REV
DATE
REASON FOR CHANGE / SUMMARY OF CHANGE
First publication
Features revision
Updates to reset values for UART Interrupt Enable register (address of 0x15) & Soft Reset and
Clock Enable register (address of 0x18); reset text correction for ICR REV register; clarification
of use of theOXCFU950 with USB hub devices
Dec 2005 7 Dec 2005
May 2006 5 May 2006
Feb 2007
DS-0023 February 2007
External—Free Release
Page 5 of 74
OXFORD [ OXFORD SEMICONDUCTOR ]
