OXFORD SEMICONDUCTOR, INC.
6.7.5
6.8
6.8.1
6.8.2
6.8.3
6.8.4
OXCFU950 DATA SHEET
I/O BASE ADDRESS REGISTER—IOBA (OFFSET 0X0A & 0X0C) ............................................................................ 26
CARD INFORMATION STRUCTURE............................................................................................................................... 26
FIXED DEFAULT CIS IMAGE....................................................................................................................................... 26
STANDARD PRE-PROGRAMMED CIS IMAGE........................................................................................................... 29
EXAMPLE USB SINGLE FUNCTION CIS IMAGE........................................................................................................ 31
EXAMPLE UART SINGLE FUNCTION CIS IMAGE ..................................................................................................... 33
7
7.1
7.2
7.3
7.4
7.5
7.6
USB HOST CONTROLLER ................................................................................................................. 35
WRITING TO AN OHCI REGISTER IN THE EMBEDDED USB HOST CONTROLLER.................................................. 37
READING FROM AN OHCI REGISTER IN THE EMBEDDED USB HOST CONTROLLER ........................................... 37
WRITING TO THE USB MEMORY ................................................................................................................................... 37
READING FROM USB MEMORY..................................................................................................................................... 38
ACCESSING USB MEMORY VIA COMMON MEMORY ACCESS.................................................................................. 38
USB HOST CONTROLLER OVERVIEW.......................................................................................................................... 38
8
UART INTERFACE.............................................................................................................................. 39
MODE SELECTION .......................................................................................................................................................... 39
450 MODE..................................................................................................................................................................... 39
550 MODE..................................................................................................................................................................... 39
750 MODE..................................................................................................................................................................... 39
650 MODE..................................................................................................................................................................... 39
950 MODE..................................................................................................................................................................... 40
REGISTER DESCRIPTION TABLES ............................................................................................................................... 41
RESET CONFIGURATION ............................................................................................................................................... 45
HOST RESET ............................................................................................................................................................... 45
SOFTWARE RESET ..................................................................................................................................................... 45
TRANSMITTER & RECEIVER FIFOS .............................................................................................................................. 45
4-BYTE ACCESS TO THR & RHR ............................................................................................................................... 45
FIFO CONTROL REGISTER—FICR ............................................................................................................................ 46
LINE CONTROL & STATUS............................................................................................................................................. 47
FALSE START BIT DETECTION.................................................................................................................................. 47
LINE CONTROL REGISTER—LCR.............................................................................................................................. 47
LINE STATUS REGISTER—LSR ................................................................................................................................. 48
UART INTERRUPTS......................................................................................................................................................... 49
INTERRUPT ENABLE REGISTER—IER...................................................................................................................... 49
INTERRUPT STATUS REGISTER—ISR...................................................................................................................... 50
INTERRUPT DESCRIPTION ........................................................................................................................................ 50
UART POWER SAVING ............................................................................................................................................... 51
MODEM INTERFACE ....................................................................................................................................................... 51
MODEM CONTROL REGISTER—MCR....................................................................................................................... 51
MODEM STATUS REGISTER—MSR .......................................................................................................................... 52
OTHER STANDARD REGISTERS ................................................................................................................................... 52
DIVISOR LATCH REGISTERS—DLL & DLM............................................................................................................... 52
SCRATCH PAD REGISTER—SPR .............................................................................................................................. 52
AUTOMATIC FLOW CONTROL....................................................................................................................................... 53
ENHANCED FEATURES REGISTER—EFR................................................................................................................ 53
SPECIAL CHARACTER DETECTION .......................................................................................................................... 54
AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 54
AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 54
BAUD RATE GENERATION............................................................................................................................................. 55
GENERAL OPERATION ............................................................................................................................................... 55
CLOCK PRESCALER REGISTER—CPR..................................................................................................................... 55
TIMES CLOCK REGISTER—TCR................................................................................................................................ 55
ALTERNATIVE BAUD RATE CONTROL REGISTERS................................................................................................ 56
ADDITIONAL FEATURES ................................................................................................................................................ 57
ADDITIONAL STATUS REGISTER—ASR ................................................................................................................... 57
FIFO FILL LEVELS—TFL & RFL .................................................................................................................................. 57
External—Free Release
Page 4 of 74
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.2
8.3
8.3.1
8.3.2
8.4
8.4.1
8.4.2
8.5
8.5.1
8.5.2
8.5.3
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.7.1
8.7.2
8.8
8.8.1
8.8.2
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.11
8.11.1
8.11.2
DS-0023 February 2007
OXFORD [ OXFORD SEMICONDUCTOR ]
