OXCB950 参数 Datasheet PDF下载

OXFORD SEMICONDUCTOR LTD.

OXCB950

C

ONTENTS

1

1.1

PERFORMANCE COMPARISON............................................................................................................ 5

IMPROVEMENTS OF THE OXCB950 OVER DISCRETE SOLUTIONS: .......................................................................... 5

2

3

4

5

6

6.1

6.2

6.2.1

6.3

6.3.1

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.5

6.6

6.6.1

6.6.2

6.6.3

6.7

6.8

BLOCK DIAGRAM ................................................................................................................................... 6

PIN INFORMATION.................................................................................................................................. 7

PIN DESCRIPTIONS ................................................................................................................................ 8

CONFIGURATION & OPERATION ....................................................................................................... 12

PCI TARGET CONTROLLER ................................................................................................................ 13

OPERATION ..................................................................................................................................................................... 13

CONFIGURATION SPACE ............................................................................................................................................... 14

CARDBUS / PCI CONFIGURATION SPACE REGISTER MAP ................................................................................... 14

ACCESSING THE UART FUNCTION............................................................................................................................... 16

CARDBUS/PCI ACCESS TO THE INTERNAL UART .................................................................................................. 16

ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 17

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 17

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 18

UART MIRROR REGISTER ‘UMR’ (OFFSET 0X08):................................................................................................... 19

GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X0C) ............................................... 20

CARDBUS/ PCI INTERRUPT ........................................................................................................................................... 21

CARDBUS/PCI POWER MANAGEMENT ........................................................................................................................ 22

POWER MANAGEMENT VIA UART/ MIO PINS .......................................................................................................... 22

POWER REPORTING .................................................................................................................................................. 23

CARDBUS POWER MANAGEMENT ........................................................................................................................... 24

CARDBUS STATUS REGISTERS.................................................................................................................................... 25

CARDBUS TUPLE INFORMATION.................................................................................................................................. 27

7

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.2

7.3

7.3.1

7.3.2

7.4

7.4.1

7.5

7.5.1

7.5.2

7.5.3

7.6

7.6.1

7.6.2

7.6.3

INTERNAL 950 UART............................................................................................................................ 28

OPERATION – MODE SELECTION ................................................................................................................................. 28

450 MODE..................................................................................................................................................................... 28

550 MODE..................................................................................................................................................................... 28

750 MODE..................................................................................................................................................................... 28

650 MODE..................................................................................................................................................................... 28

950 MODE..................................................................................................................................................................... 29

REGISTER DESCRIPTION TABLES ............................................................................................................................... 30

RESET CONFIGURATION ............................................................................................................................................... 34

HARDWARE RESET .................................................................................................................................................... 34

SOFTWARE RESET ..................................................................................................................................................... 34

TRANSMITTER AND RECEIVER FIFOS ......................................................................................................................... 35

FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 35

LINE CONTROL & STATUS............................................................................................................................................. 36

FALSE START BIT DETECTION.................................................................................................................................. 36

LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 36

LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 37

INTERRUPTS & SLEEP MODE........................................................................................................................................ 38

INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 38

INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 39

INTERRUPT DESCRIPTION ........................................................................................................................................ 39

External-Free Release

Page 2

DS-0033 Sep 05