OXFORD SEMICONDUCTOR LTD.
OX9160
3
P
IN
D
ESCRIPTIONS
11
Dir
Name
Description
Mode
00
01
PCI Interface
139, 140, 141, 143, 144, 145,
148, 149, 152, 154, 155, 156,
159, 160, 1, 2, 14, 15, 16, 19,
20, 23, 24, 26, 28, 29, 32, 33,
34, 36, 37, 38
P_I/O
AD[31:0]
Multiplexed PCI Address/Data bus
150, 3, 13, 27
136
4
7
5
6
9
12
11
10
151
134
132
138
Local bus
122
N/A
122
123
N/A
123
102
114-7
112
113
105-8
118-21
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
O
O
O
O
O
O
O
O
Z
O
O
I/O
I/O
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA #
PME#
LBRST
LBRST#
LBDOUT
LBCS[3:0]#
LBDS[3:0]#
LBWR#
LBRDWR#
LBRD#
Hi-Z
LBA[7:0]
LBA[12:0]
LBD[7:0]
LBD[31:0]
PCI Command/Byte enable
PCI system clock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialization device select
PCI system reset
PCI interrupt
Power management event
Local bus active-high reset
Local bus active-low reset
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and low
when they are in input mode.
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local bus active-low write-strobe (Intel mode)
Local bus Read-not- Write control (Motorola mode)
Local bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
(8-bit mode) Local bus address signals
(32-bit mode) Local bus address signals
(8-bit mode) Local bus data signals
(32-bit mode) Local bus data signals
N/A
N/A
N/A
N/A
N/A
N/A
N/A
114-7
112
113
N/A
76-9,
105-8,
118-21
N/A
92-5
98-101
N/A
47-55,
58-61,
66-68,
80-87,
92-95,
98-101
N/A
Data Sheet Revision 1.22
Page 5
OXFORD [ OXFORD SEMICONDUCTOR ]
