OX9160 参数 Datasheet PDF下载

OXFORD SEMICONDUCTOR LTD.

OX9160

C

ONTENTS

1

2

3

4

4.1

4.2

4.2.1

4.3

4.3.1

4.3.2

4.3.3

4.4

4.4.1

4.4.2

4.4.3

4.4.4

4.4.5

4.5

4.6

BLOCK DIAGRAM .......................................................................................................................3

PIN INFORMATION .....................................................................................................................4

PIN DESCRIPTIONS ....................................................................................................................5

PCI TARGET CONTROLLER .......................................................................................................8

OPERATION.......................................................................................................................................................................... 8

CONFIGURATION SPACE ................................................................................................................................................... 8

PCI CONFIGURATION SPACE REGISTER MAP ........................................................................................................... 9

ACCESSING LOGICAL FUNCTIONS................................................................................................................................ 10

PCI ACCESS TO 8-BIT LOCAL BUS ............................................................................................................................. 10

PCI ACCESS TO 32-BIT LOCAL BUS ........................................................................................................................... 11

PCI ACCESS TO PARALLEL PORT .............................................................................................................................. 11

ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 12

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ......................................................... 12

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................. 13

LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): ................................................................... 14

LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): .................................................................. 16

GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ................................................ 17

PCI INTERRUPTS ............................................................................................................................................................... 18

POWER MANAGEMENT.................................................................................................................................................... 19

5

5.1

5.2

5.3

5.4

LOCAL BUS ..............................................................................................................................20

OVERVIEW.......................................................................................................................................................................... 20

OPERATION........................................................................................................................................................................ 20

CONFIGURATION & PROGRAMMING ............................................................................................................................. 21

CLOCK REFERENCES ...................................................................................................................................................... 21

6

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.2

6.3

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

BIDIRECTIONAL PARALLEL PORT...........................................................................................22

OPERATION AND MODE SELECTION ............................................................................................................................. 22

SPP MODE...................................................................................................................................................................... 22

PS2 MODE...................................................................................................................................................................... 22

EPP MODE...................................................................................................................................................................... 22

ECP MODE (NOT SUPPORTED)................................................................................................................................... 22

PARALLEL PORT INTERRUPT ......................................................................................................................................... 22

REGISTER DESCRIPTION................................................................................................................................................. 23

PARALLEL PORT DATA REGISTER ‘PDR’................................................................................................................... 23

DEVICE STATUS REGISTER ‘DSR’.............................................................................................................................. 23

DEVICE CONTROL REGISTER ‘DCR’ .......................................................................................................................... 24

EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................... 24

EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................... 24

EXTENDED CONTROL REGISTER ‘ECR’ .................................................................................................................... 24

SPECIFICATION ................................................................................................................................................................. 25

EEPROM DATA ORGANISATION ..................................................................................................................................... 25

ZONE0: HEADER............................................................................................................................................................ 25

ZONE1: LOCAL CONFIGURATION REGISTERS ......................................................................................................... 26

ZONE2: IDENTIFICATION REGISTERS........................................................................................................................ 27

ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................... 27

7

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

SERIAL EEPROM......................................................................................................................25

8

9

OPERATING CONDITIONS ........................................................................................................28

DC ELECTRICAL CHARACTERISTICS ......................................................................................28

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Data Sheet Revision 1.22