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OX16PCI954_05 参数 Datasheet PDF下载

OX16PCI954_05图片预览
型号: OX16PCI954_05
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的四通道UART和PCI接口 [Integrated Quad UART and PCI interface]
分类和应用: PC
文件页数/大小: 73 页 / 438 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OX16PCI954  
OXFORD SEMICONDUCTOR LTD.  
1 PERFORMANCE COMPARISON  
Feature  
16C554 +  
PLX9050  
16C654 +  
PLX9050  
OX16PCI954  
Internal serial channels  
Integral 1284 EPP parallel port  
Multi-function PCI device  
Support for PCI Power Management  
Zero wait-state read/write operation  
No. of available Local Bus interrupt pins  
DWORD access to UART Interrupt Source  
Registers & FIFO Levels  
Good-Data status  
4
0
0
yes  
yes  
yes  
yes1  
12  
no  
no  
no  
no  
2
no  
no  
no  
no  
2
yes  
no  
no  
yes  
yes  
yes  
no  
yes  
no  
no  
yes  
no  
Full Plug and Play with external EEPROM  
Subsystem Vendor ID & Subsystem ID with  
no external EEPROM  
External 1x baud rate clock  
Max baud rate in normal mode  
Max baud rate in 1x clock mode  
FIFO depth  
yes  
15 Mbps  
60 Mbps  
128  
no  
115 Kbps  
n/a  
16  
no  
1.5 Mbps  
n/a  
64  
Sleep mode  
Auto Xon/Xoff flow  
Auto CTS#/RTS# flow  
Auto DSR#/DTR# flow  
yes  
yes  
yes  
yes  
no  
no  
no  
no  
yes  
yes  
yes  
no  
No. of Rx interrupt thresholds  
No. of Tx interrupt thresholds  
No. of flow control thresholds  
Transmitter empty interrupt  
Readable status of flow control  
Readable FIFO levels  
128  
128  
128  
yes  
yes  
yes  
4
1
n/a  
no  
no  
4
4
4
no  
no  
no  
no  
Clock prescaler options  
Rx/Tx disable  
248  
yes  
n/a  
no  
2
no  
Software reset  
yes  
no  
no  
Device ID  
yes  
no  
no  
9-bit data frames  
yes  
no  
no  
RS485 buffer enable  
yes  
no  
no  
Infra-red (IrDA)  
yes  
no  
yes  
Table 1: OX16PCI950 performance compared with PLX + generic UART combinations  
Note 1:  
Zero wait-state applies only to internal UARTs  
Improvements of the OX16PCI954 over discrete solutions:  
Higher degree of integration:  
OX16PCI954 offers four internal 16C950 high-performance  
transaction to an internal UART can complete within four  
PCI clock cycles.  
UARTs and one bi-directional parallel port.  
Reduces interrupt latency:  
Improved access timing:  
OX16PCI954 offers shadowed FIFO levels and Interrupt  
status registers of internal UARTs, and Interrupt Status of  
internal UARTs and MIO pins to reduce the device driver  
interrupt latency.  
Access to internal UARTs require zero or one PCI wait  
states. A PCI read transaction from an internal UART can  
complete within five PCI clock cycles and a write  
DS-0029 Jul 05  
External—Free Release  
Page 6