OXFORD SEMICONDUCTOR LTD.
OX16PCI954
1
P
ERFORMANCE
C
OMPARISON
Feature
Internal serial channels
Integral 1284 EPP parallel port
Multi-function PCI device
Support for PCI Power Management
Zero wait-state read/write operation
No. of available Local Bus interrupt pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
Subsystem Vendor ID & Subsystem ID with
no external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OX16PCI954
4
yes
yes
yes
yes
1
12
yes
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C554 +
PLX9050
0
no
no
no
no
2
no
no
yes
no
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C654 +
PLX9050
0
no
no
no
no
2
no
no
yes
no
no
1.5 Mbps
n/a
64
yes
yes
yes
no
4
4
4
no
no
no
2
no
no
no
no
no
yes
Table 1: OX16PCI950 performance compared with PLX + generic UART combinations
Note 1:
Zero wait-state applies only to internal UARTs
Improvements of the OX16PCI954 over discrete solutions:
Higher degree of integration:
OX16PCI954 offers four internal 16C950 high-performance
UARTs and one bi-directional parallel port.
Improved access timing:
Access to internal UARTs require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
DS-0029 Jul 05
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
OX16PCI954 offers shadowed FIFO levels and Interrupt
status registers of internal UARTs, and Interrupt Status of
internal UARTs and MIO pins to reduce the device driver
interrupt latency.
Page 6
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