OX16PCI954
OXFORD SEMICONDUCTOR LTD.
7.5.2
7.5.3
7.6
7.6.1
7.6.2
7.6.3
7.6.4
7.7
7.7.1
7.7.2
7.8
7.8.1
7.8.2
7.9
LINE CONTROL REGISTER ‘LCR’ ........................................................................................................................ 36
LINE STATUS REGISTER ‘LSR’............................................................................................................................ 37
INTERRUPTS & SLEEP MODE................................................................................................................................. 38
INTERRUPT ENABLE REGISTER ‘IER’................................................................................................................. 38
INTERRUPT STATUS REGISTER ‘ISR’................................................................................................................. 39
INTERRUPT DESCRIPTION.................................................................................................................................. 39
SLEEP MODE ....................................................................................................................................................... 40
MODEM INTERFACE................................................................................................................................................ 40
MODEM CONTROL REGISTER ‘MCR’.................................................................................................................. 40
MODEM STATUS REGISTER ‘MSR’ ..................................................................................................................... 41
OTHER STANDARD REGISTERS............................................................................................................................. 41
DIVISOR LATCH REGISTERS ‘DLL & DLM’ .......................................................................................................... 41
SCRATCH PAD REGISTER ‘SPR’......................................................................................................................... 41
AUTOMATIC FLOW CONTROL ................................................................................................................................ 42
ENHANCED FEATURES REGISTER ‘EFR’ ........................................................................................................... 42
SPECIAL CHARACTER DETECTION.................................................................................................................... 43
AUTOMATIC IN-BAND FLOW CONTROL.............................................................................................................. 43
AUTOMATIC OUT-OF-BAND FLOW CONTROL.................................................................................................... 43
7.9.1
7.9.2
7.9.3
7.9.4
7.10 BAUD RATE GENERATION...................................................................................................................................... 44
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
GENERAL OPERATION........................................................................................................................................ 44
CLOCK PRESCALER REGISTER ‘CPR’................................................................................................................ 44
TIMES CLOCK REGISTER ‘TCR’ .......................................................................................................................... 44
EXTERNAL 1X CLOCK MODE .............................................................................................................................. 46
CRYSTAL OSCILLATOR CIRCUIT ........................................................................................................................ 46
7.11 ADDITIONAL FEATURES ......................................................................................................................................... 46
7.11.1
7.11.2
7.11.3
7.11.4
7.11.5
7.11.6
7.11.7
7.11.8
7.11.9
ADDITIONAL STATUS REGISTER ‘ASR’............................................................................................................... 46
FIFO FILL LEVELS ‘TFL & RFL’............................................................................................................................. 47
ADDITIONAL CONTROL REGISTER ‘ACR’ ........................................................................................................... 47
TRANSMITTER TRIGGER LEVEL ‘TTL’ ................................................................................................................ 48
RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ................................................................................................. 48
FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’ .............................................................................................................. 48
DEVICE IDENTIFICATION REGISTERS................................................................................................................ 48
CLOCK SELECT REGISTER ‘CKS’ ....................................................................................................................... 49
NINE-BIT MODE REGISTER ‘NMR’....................................................................................................................... 49
7.11.10 MODEM DISABLE MASK ‘MDM’............................................................................................................................ 50
7.11.11 READABLE FCR ‘RFC’.......................................................................................................................................... 50
7.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.............................................................................................................. 50
8
LOCAL BUS...............................................................................................................................................51
OVERVIEW ............................................................................................................................................................... 51
OPERATION ............................................................................................................................................................. 51
CONFIGURATION & PROGRAMMING...................................................................................................................... 52
8.1
8.2
8.3
9
BIDIRECTIONAL PARALLEL PORT.......................................................................................................53
OPERATION AND MODE SELECTION ..................................................................................................................... 53
SPP MODE ........................................................................................................................................................... 53
PS2 MODE............................................................................................................................................................ 53
EPP MODE ........................................................................................................................................................... 53
ECP MODE (NOT SUPPORTED) .......................................................................................................................... 53
PARALLEL PORT INTERRUPT ................................................................................................................................ 53
REGISTER DESCRIPTION........................................................................................................................................ 54
PARALLEL PORT DATA REGISTER ‘PDR’ ........................................................................................................... 54
DEVICE STATUS REGISTER ‘DSR’ ...................................................................................................................... 54
DEVICE CONTROL REGISTER ‘DCR’................................................................................................................... 55
EPP ADDRESS REGISTER ‘EPPA’....................................................................................................................... 55
EPP DATA REGISTERS ‘EPPD1-4’....................................................................................................................... 55
EXTENDED CONTROL REGISTER ‘ECR’............................................................................................................. 55
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
Data Sheet Revision 1.3
Page 3
OXFORD [ OXFORD SEMICONDUCTOR ]
