OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Mode
Dir1
Name
Description
00
01
10
11
Serial port pins
81, 78, 58, 53
N/A
O
RTS[3:0]#
Active-low modem request-to-send output. If automated
RTS# flow control is enabled, the RTS# pin is deasserted
and reasserted whenever the receiver FIFO reaches or falls
below the programmed thresholds, respectively.
83, 76, 60, 51
84, 75, 61, 50
N/A
N/A
I
I
CTS[3:0]#
DSR[3:0]#
Active-low modem clear-to-send input. If automated CTS#
flow control is enabled, upon deassertion of the CTS# pin,
the transmitter will complete the current character and enter
the idle mode until the CTS# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the CTS# pin.
Active-low modem data-set-ready input. If automated DSR#
flow control is enabled, upon deassertion of the DSR# pin,
the transmitter will complete the current character and enter
the idle mode until the DSR# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the DSR# pin
I
I
I
Rx_Clk_In[3:0]
RI[3:0]#
External receiver clock for isochronous applications. The
Rx_Clk_In is selected when CKS[1:0] = ‘01’.
Active-low modem Ring-Indicator input
86, 73, 67, 48
N/A
Tx_Clk_In[3:0]
External transmitter clock. This clock can be used by the
transmitter (and indirectly by the receiver) when CKS[6]=’1’.
Crystal oscillator output
Crystal oscillator input or external clock pin. Maximum
frequency 60MHz
64
63
N/A
N/A
O
I
XTLO
XTLI
8-bit local bus
71
N/A
O
UART_Clk_Out Buffered crystal output. This clock can drive external UARTs
connected to the local bus. Can be enabled / disabled by
software.
122
123
N/A
N/A
O
O
O
LBRST
LBRST#
LBDOUT
Local bus active-high reset
Local bus active-low reset
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
102
N/A
See
32-bit
Local
bus
109
114-7
N/A
N/A
O
O
LBCLK
LBCS[3:0]#
Buffered PCI clock. Can be enabled / disabled by software
Local bus active-low Chip-Select (Intel mode)
O
O
LBDS[3:0]#
LBWR#
Local bus active-low Data-Strobe (Motorola mode)
Local Bus active-low write-strobe (Intel mode)
112
113
N/A
N/A
O
O
LBRDWR#
LBRD#
Local Bus Read-not-Write control (Motorola mode)
Local Bus active-low read-strobe (Intel mode)
Z
O
Hi-Z
LBA[7:0]
Permanent high impedance (Motorola mode)
Local bus address signals
105-8
118-21
92-5
N/A
N/A
I/O
LBD[7:0]
Local bus data signals
98-101
Data Sheet Revision 1.3
Page 9
OXFORD [ OXFORD SEMICONDUCTOR ]
