Figure 3. Character set—DLX3416
The waveforms of Figure 4 demonstrate the relation-
ships of the signals required to generate a write cycle.
(Check individual data sheet for minimum values). As can
be seen from the waveforms, all signals are referenced
from the rising or trailing edge of write.
D0
D1
D2
D3
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
ASCII
CODE
D6 D5 D4 HEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
Cursor
The DLX3416 cursor function causes all dots to light
at 50% brightness. The cursor can be used to indicate
the position in the display of the next character to be
entered. The cursor is not a character but overrides
the display of a stored character. Upon removal of the
cursor, the display will again show the character
stored in memory.
The cursor can be written into any digit position by set-
ting the cursor enable (CUE) high, setting the digit
address (A1, A0), enabling Chip Enable, (CE1, CE2), cur-
sor select (CU), Write (WR) and Data (D0). A high on data
line D0 will place a cursor into the position set by the
address A0 and A1. Conversely, a low on D0 will remove
the cursor. The cursor will remain displayed after the cur-
sor (CU) and write (WR) signals have been removed.
During the cursor-write sequence, data lines D1 through
D6 are ignored by the 3416.
Notes: 1. High = 1 level.
2. Low = 0 level.
3. Upon power up, the device will initialize in a random state.
Clear Memory
If the user does not wish to utilize the cursor function,
the cursor enable (CUE) can be tied low to disable the
cursor function. A flashing cursor can be realized by sim-
ply pulsing the CUE line after cursor data has been
stored.
Clearing of the entire internal four digit memory may be accomplished by
holding the clear line (CLR) low for one complete internal display multi-
plex cycle, 15 mS minimum for DL 3416, 1 mS for DLX3416. Less time
may leave some data uncleared. CLR also clears the cursor memory.
General Design Considerations
Display Blanking
Using Positive true logic, address order is from right to
left. For left to right address order, use the “ones com-
plement” or simple inversion of the addresses.
Blanking the display may be accomplished by loading a blank, space or
illegal code into each digit of the display or by using the (BL) display
blank input. Setting the (BL) input low does not affect the contents of
either data or cursor memory. A flashing display can be realized by
pulsing (BL).
For systems with only a 6 bit (abbreviated ASCII) code
format, Data Line D6 cannot be left open. Data D6 must
be the complement of Data Line D5.
Operation
A “display test” or “lamp test” function can be achieved
by simply storing a cursor into all digits.
Multiplexed display systems sequentially read and display data from a
memory device. In synchronous systems, control circuitry must com-
pare the location of data to be read to the location or position of new
data to be stored or displayed, i.e., synchronize before a Write can be
done. This can be slow and cumbersome.
Because of the random state of the cursor RAM after
power up, if the cursor function is to be used, it will be
necessary to clear cursors initially to assure that all cur-
sor memories contain its zero state. This is easily
accomplished with the CLR input.
Data entry in Intelligent Displays is asynchronous and may be done in
any random order. Loading data is similar to writing into a RAM. Each
digit has its own memory location and will display until replaced by
another code.
When using the 3416 on a separate display board having
more than 6 inches of cable length, it may be necessary
to buffer all inputs. This is most easily achieved with Hex
non-inverting buffers such as the 74365. The object is to
prevent transient current in the protection diodes. The
buffers should be located on the display board near
the displays.
Figure 4. Write cycle waveforms
t
t
AH
AS
CU,A0,A1
CE1,CE2
4 V
2 V
0 V
Local power supply bypass capacitors are also needed in
many cases. These should be 6 or 10 volt, tantalum type
with 10 µF or greater capacitance. Low internal resis-
tance is important due to current steps which result
from the internal multiplexing of the displays.
t
DS
4 V
2 V
0 V
Data 0–6
t
W
t
DH
4 V
2 V
0 V
If small wire cables are used, it is good engineering prac-
tice to calculate the wire resistance of the ground plus
the +5 volt wires. More than 0.1 volt drop, (at 25 mA per
WR
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
Appnote 17
3
May 31, 2000-12
OSRAM [ OSRAM GMBH ]
