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Internal Synchronized Slop Compensation
Although there are more advantages of the current mode control than conventional voltage mode control, there are still several
drawbacks of peak-sensing current-mode converter, especially the open loop instability when it operates in higher than 50% of
the duty-cycle. To solve this problem, the RS2051 is introduced an internal slope compensation adding voltage ramp to the
current sense input voltage for PWM generation. It improves the close loop stability greatly at CCM, prevents the sub-harmonic
oscillation and thus reduces the output ripple voltage.
V
SLOP
=
0.33
×
DUTY
=
0.4389
×
DUTY
DUTY
MAX
Slop Compensation
Current Sensing & Dynamic peak limiting
The current flowing by the power MOSFET comes into being a voltage V
SENSE
on the Sense pin cycle-by-cycle, which compares
to the internal reference voltage, and controls the reverse of the internal register, limits the peak current IMAX of the primary of
1
2
×
L
×
I
MAX
. So adjusting the R
SENSE
can set the maximal output power of
2
V
IN
the power supple. The current flowing by the power MOSFET has an extra value (
Δ
I
=
×
T
D
) due to the system delay
L
P
the transformer. The transformer energy is
E
=
time that is from detecting the current through the Sense pin to power MOSFET off in the RS2051 (Among these, V
IN
is the
primary winding voltage of the transformer and L
P
is the primary wind inductance). V
IN
ranges from 85VAC to 264VAC. To
guarantee the output power is a constant for universal input AC voltage, there is a dynamic peak limit circuit to compensate the
system delay T that the system delay brings on.
IPEAK
MAX
=
IPEAK
MAX
Soft Start
0.65
V
(
V
IN
=
264
V
)
R
SENSE
0.85
V
=
(
V
IN
=
85
V
)
R
SENSE
The RS2051 features an internal soft start during the initial power on. As soon as VDD reaches ON, the voltage on the internal
fixed capacitor is gradually increased from zero up to the maximum internal clamping level. The time of the soft start is fixed
about 1.2mS for the constant charge current and the fixed capacitor.
Frequency Jitter
The frequency jittering is introduced in the RS2051. As following figure, the internal oscillation frequency is modulated by itself.
A whole surge cycle includes 8 pulses and the jittering ranges from -4% to +4%. Thus, the function could minimize the
electromagnetic interferer from the power supply module.
Frequency Jitter
DS-RS2051-02
September, 2007
www.Orister.com
ORISTER [ ORISTER CORPORATION ]
