FS6182
VCXO Clock Generator IC
Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
IDD
fXTAL = 13.5MHz; CL = 10pF
Fundamental Mode
20
mA
Voltage Controlled Crystal Oscillator
Crystal Resonator Frequency
fXTAL
CL(xtal)
C1(xtal)
5
13.5
20
18
MHz
pF
As seen by a crystal connected to XIN and
XOUT (@ VXTUNE = mid-range)
Crystal Loading Capacitance
Crystal Resonator Motional Capacitance
VCXO Tuning Range
20
fF
ppm
ppm/V
uW
fXTAL = 13.5MHz; CL = 20pF; CMOT = 25fF
Note: positive delta F for positive delta V
RXTAL=20 ohm; CL = 20pF
300
100
200
VCXO Tuning Characteristic
Crystal Drive Level
Clock Outputs (CLKA, CLKB, CLKC)
High-Level Output Source Current *
Low-Level Output Sink Current *
IOH
IOL
VO = 2.0V
40
17
25
25
55
55
mA
mA
VO = 0.4V
zOH
zOL
IOSH
IOSL
VO = 0.1VDD; output driving high
VO = 0.1VDD; output driving low
VO = 0V; shorted for 30s, max.
VO = 3.3V; shorted for 30s, max.
Output Impedance *
Ω
Short Circuit Source Current *
Short Circuit Sink Current *
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Clock Outputs (CLKx)
Duty Cycle *
thi / tclk; Measured at VDD/2
43
57
%
From rising edge to next rising edge at VDD/2, CL =
10pF
Jitter, Absolute Period (pk-pk) *
150
ps
tj(∆P)
Rise Time *
tr
tf
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
(unless otherwise noted in Frequency Table)
From power valid
1
1
ns
ns
Fall Time *
Output Frequency Synthesis Error
VCXO Stabilization Time *
PLL Stabilization Time *
0
ppm
ms
us
tVCXOSTB
tPLLSTB
10
From VCXO stable
500
4
2.27.02
ISO9001
ONSEMI [ ONSEMI ]
