FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
4.2.2 Phase Alignment
To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The
source for the feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider
must be dividing at a multiple of the post divider.
Reference
Divider (NR)
Phase
Frequency
Detect
fIN
Post
Divider (NF)
VCO
fOUT
fIN
Feedback
Divider (NF)
fOUT
Figure 7: Aligned I/O Phase
4.2.3 Phase Sampling and Initial Alignment
However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the
initial synchronization of the output phase to input phase, a phase align "flag" makes a transition (zero to one or one to zero) when the
output clock phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input
clock phase.
First, the FS6131 is used to sample the output clock with the feedback source clock and set/clear the phase align flag when the two
clocks match to within a feedback source clock period. Then, the clock gobbler is used to delay the output phase relative to the input
phase one VCO clock at a time until a transition on the flag occurs. When a transition occurs, the output and input clocks are phase
aligned.
To enter this mode, set STAT[1] to one and clear STAT[0] to zero. If the CMOS bit is set to one, the LOCK/IPRG pin can display the
flag. The flag is always available under software control by reading back the STAT[1] bit, which will be overwritten by the flag in this
mode.
4.2.4 Feedback Divider Monitoring
The feedback divider clock can be brought out the LOCK/IPRG pin independent of the output clock to allow monitoring of the feedback
divider clock. To enter this mode, set both the STAT[1] and STAT[0] bits to one. The CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
AMI Semiconductor – Rev. 3.0, Jan. 08
6
www.amis.com
Specifications subject to change without notice
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