FEDL9222-02
ML9222
¡ Semiconductor
Output Timing (Duplex Operation)
*1bit time=4/f
OSC
(The dimming data is 64/1024)
2048bit times (1 display cycle)
VDD
64bit times
64bit times
GRID1
GRID2
GRID3
D-GND
960bit times
960bit times
960bit times
VDD
64bit times
D-GND
VDD
D-GND
VDD
3bit times 957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
67bit times
67bit times
67bit times
1981bit times
67bit times
67bit times
67bit times
67bit times
1981bit times
SEG1-32
D-GND
5 V
957bit times
67bit times
DIM OUT
L-GND
5 V
957bit times
67bit times
SYNC OUT1
SYNC OUT2
L-GND
5 V
957bit times
1981bit times
L-GND
Output Timing (Triplex Operation)
*1bit time=4/f
OSC
(The dimming data is 64/1024)
3072bit times (1 display cycle)
VDD
64bit times
GRID1
D-GND
VDD
960bit times
960bit times
64bit times
GRID2
D-GND
VDD
960bit times
64bit times
GRID3
D-GND
VDD
3bit times 957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
67bit times
SEG1-32
67bit times
67bit times
67bit times
67bit times
67bit times
67bit times
D-GND
5 V
957bit times
957bit times
957bit times
957bit times
67bit times
DIM OUT
L-GND
5 V
957bit times
67bit times
1981bit times
67bit times
SYNC OUT1
SYNC OUT2
L-GND
5 V
957bit times
1981bit times
L-GND
12/25
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