FEDL9222-02
ML9222
¡ Semiconductor
Output Timing (Duplex Operation)
*1bit time=4/f
OSC
(The dimming data is 1016/1024)
2048bit times (1 display cycle)
VDD
1016bit times
1016bit times
8bit times
GRID1
GRID2
GRID3
D-GND
8bit times
1016bit times
8bit times
VDD
D-GND
VDD
D-GND
3bit times
5bit times
5bit times
5bit times
VDD
1019bit times
1019bit times
1019bit times
1029bit times
1019bit times
5bit times
1019bit times
5bit times
SEG1-32
D-GND
5bit times
5 V
1019bit times
5bit times
1019bit times
5bit times
DIM OUT
L-GND
5bit times
5 V
1029bit times
5bit times
1019bit times
5bit times
SYNC OUT1
SYNC OUT2
L-GND
5bit times
5 V
1019bit times
1029bit times
L-GND
Output Timing (Triplex Operation)
*1bit time=4/f
OSC
(The dimming data is 1016/1024)
3072bit times (1 display cycle)
VDD
1016bit times
GRID1
D-GND
8bit times
8bit times
VDD
1016bit times
GRID2
D-GND
VDD
8bit times
1016bit times
5bit times
GRID3
D-GND
3bit times
5bit times
5bit times
VDD
1019bit times
SEG1-32
1019bit times
5bit times
1019bit times
5bit times
D-GND
5bit times
5 V
1019bit times
DIM OUT
1019bit times
5bit times
1019bit times
5bit times
L-GND
5bit times
5 V
1019bit times
SYNC OUT1
1029bit times
5bit times
1019bit times
5bit times
L-GND
5bit times
5 V
1029bit times
SYNC OUT2
1019bit times
1019bit times
L-GND
11/25
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