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ML9044A-XXACVWA 参数 Datasheet PDF下载

ML9044A-XXACVWA图片预览
型号: ML9044A-XXACVWA
PDF下载: 下载PDF文件 查看货源
内容描述: 点阵LCD控制器驱动程序 [DOT MATRIX LCD CONTROLLER DRIVER]
分类和应用: 显示控制器微控制器和处理器外围集成电路驱动时钟
文件页数/大小: 64 页 / 689 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDL9044A-04  
OKI Semiconductor  
ML9044A-xxA/xxB  
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)  
Applicable  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
pins  
Voltage Multiplier  
Input Voltage  
VMUL  
Note 7  
2.7  
3.5  
V
VDD–VIN  
VDD = 2.7 V, VIN = 0 V  
f = 125 kHz  
(VDD–VIN)  
1/5 bias  
1/4 bias  
4.1  
3.9  
× 2  
Voltage Multiplier  
Output Voltage  
A capacitor for the voltage  
multiplier =1 to 4.7 µF  
V5OUT  
V
VDD–V5IN  
(VDD–VIN)  
No load  
× 2  
BE = “H”  
VDD = 5 V, V5IN = –2 V, 1/5 bias,  
Contrast data: 1F, No load  
6.6  
6.6  
3.8  
3.6  
4.0  
3.6  
2.2  
1.9  
VDD = 5 V, V5IN = –2 V, 1/4 bias,  
Contrast data: 1F, No load  
VLCD  
MAX  
V
VDD = 4.1 V, V5IN = 0 V, 1/5 bias,  
Contrast data: 1F, No load  
Maximum and  
minimum LCD  
drive voltages  
when internal  
VDD = 3.9 V, V5IN = 0 V, 1/4 bias,  
Contrast data: 1F, No load  
VDD–V5  
VDD = 5 V, V5IN = –2 V, 1/5 bias,  
Contrast data: 00, No load  
4.6  
4.2  
2.8  
2.5  
variable resistors  
are used. Note 8  
VDD = 5 V, V5IN = –2 V, 1/4 bias,  
Contrast data: 00, No load  
VLCD  
MIN  
V
V
VDD = 4.1 V, V5IN = 0 V, 1/5 bias,  
Contrast data: 00, No load  
VDD = 3.9 V, V5IN = 0 V, 1/4 bias,  
Contrast data: 00, No load  
VLCD1  
VLCD2  
1/5 bias  
3.3  
3.3  
7.0  
7.0  
Bias Voltage for  
Driving LCD  
VDD–V5  
Note 9  
V5  
1/4 bias  
Note 1: Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the  
common pins (COM1 to COM17) when the current of 4 µA flows in or flows out at one common  
pin.  
Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and V5 pins and  
any of the segment pins (SEG1 to SEG120) when the current of 4 µA flows in or flows out at one  
common pin.  
The current of 4 µA flows out when the output level is VDD or flows in when the output level is  
V5.  
Note 2: Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is  
fed to the internal Rf oscillation or OSC1 under the following conditions:  
VDD = 5 V  
GND = V5 = 0 V,  
V1, V2, V3A (V3B) and V4: Open  
E, SSR, CSR, and BE: “L” (fixed)  
Other input pins: “L” or “H” (fixed)  
Other output pins: No load  
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