FEDL87V2107-01
OKI Semiconductor
ML87V2107
VBID Initial value: 0, Setting range: 0 to 1
Sets the valid number of VBI data lines.
In 625- or 525-line input format, the effective numbers of lines are 288 and 243. When input/output is in
ITU-R BT.656 mode, the number of memory write lines are 304 and 254. To make VBI data as effective
data also, select this setting. However, vertical direction phase adjustment cannot be set.
Table R2-2-1(3) Setting the Number of Memory Write Lines
VBID
625-line mode
288 lines
525-line mode
243 lines
0
1
304 lines
254 lines
ICINV Initial value: 0; Setting range: 0 to 1
Sets internal input system clock (IICLK) polarity.
Sets the polarity of IICLK (ICLK frequency-divided by 2) generated in the input 8-bit mode and ITU-R
BT.656 mode.
This setting is not in synchronization with IVS.
Table R2-2-1 (4) IICLK Polarity Setting
ICINV
IICLK polarity
0
At IHS rise reset: 1
At IHS rise reset: 0
1
IHES Initial value: 0; Setting range: 0 to 1
Sets IHS edge for internal input system clock (IICLK) reset
Selects the reset timing of IICLK generated in 1H period at the fall or rise of IHS.
Table R2-2-1 (5) IHS Edge Setting for IICLK Reset
IHES
IHS edge for H reset
0
Rise
1
Fall
POFF Initial value: 0; Setting range: 0 to 1
Sets ITU-R BT.656 mode parity check.
Table R2-2-1 (6) ITU-R BT.656 Mode Parity Check Setting
POFF
Parity check
ON
0
1
OFF
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