PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
No.
80
81
82
83
Symbol
VDD
I/O
—
—
I
Pad Remarks
Pin Description
Power supply 3.3 V
Ground
VSS
MTEST7
MTEST6
pull-down 50k
pull-down 50k
Memory test input pin – bit 7 (1: test mode)
Memory test input pin – bit 6 (1: test mode)
Output enable input pin (normally set to 1)
0: YO[7:0], CO[7:0] disable (Hi-z)
I
84
OE
I
pull-down 50k
1: YO[7:0], CO[7:0] enable (drive)
Equivalent operation to setting fixed to 1 in RESET=0 or DNR=1
Unused pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
N.C.
N.C.
—
—
—
—
I
Unused pin
N.C.
Unused pin
N.C.
Unused pin
TEST5
VDD
pull-down 50k
Test input pin – bit 5 (1: test mode)
Power supply 3.3 V
—
I
TEST4
TEST3
TEST2
TEST1
MTEST5
MTEST4
MTEST3
MTEST2
MTEST1
VSS
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
Test input pin – bit 4 (1: test mode)
Test input pin – bit 3 (1: test mode)
Test input pin – bit 2 (1: test mode)
Test input pin – bit 1 (1: test mode)
Memory test input pin – bit 5 (1: test mode)
Memory test input pin – bit 4 (1: test mode)
Memory test input pin – bit 3 (1: test mode)
Memory test input pin – bit 2 (1: test mode)
Memory test input pin – bit 1 (1: test mode)
Ground
I
I
I
I
I
I
I
I
—
Notes: In 8-bit YcbCr and ITU-R BT. 656 mode, CI0-7 pin should be connected to the Vss level.
6/13
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