PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
No.
42
Symbol
VDD
I/O
—
Pad Remarks
Pin Description
Power supply 3.3 V
Noise reduction output mode setting pin
pull-down 50k 0: Normal operation
1: Direct noise reduction mode
Unused pin
43
DNR
I
44
45
N.C.
SSG
—
I
pull-down 50k Internally generated sync signal mode setting pin
Output system sync signal input/output select setting pin
pull-down 50k 0: OVS, OHS input mode
46
INT
I
1: OVS, OHS internally generated output mode
Schmitt(IN)
47
48
OHS
OVS
I/O
I/O
Output system horizontal sync signal input/output pin
pull-down 50k
Schmitt(IN)
Output system vertical sync signal input/output pin
pull-down 50k
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
HREF
VSS
O
—
—
O
O
O
O
—
O
O
O
O
—
I
Data output horizontal reference signal output pin
Ground
VDD
Power supply 3.3 V
CO0
CO1
CO2
CO3
VSS
Chrominance signal output pin – bit 0 (LSB)
Chrominance signal output pin – bit 1
Chrominance signal output pin – bit 2
Chrominance signal output pin – bit 3
Ground
CO4
CO5
CO6
CO7
VDD
Chrominance signal output pin – bit 4
Chrominance signal output pin – bit 5
Chrominance signal output pin – bit 6
Chrominance signal output pin – bit 7(MSB)
Ground
OCLK
VSS
Output system clock pin
—
O
O
O
O
—
O
O
O
O
—
—
—
—
—
—
Ground
YO0
YO1
YO2
YO3
VDD
YO4
YO5
YO6
YO7
VSS
Luminance signal output pin – bit 0 (LSB)
Luminance signal output pin – bit 1
Luminance signal output pin – bit 2
Luminance signal output pin – bit 3
Power supply 3.3 V
Luminance signal output pin – bit 4
Luminance signal output pin – bit 5
Luminance signal output pin – bit 6
Luminance signal output pin – bit 7 (MSB)
Ground
N.C.
N.C.
N.C.
N.C.
N.C.
Unused pin
Unused pin
Unused pin
Unused pin
Unused pin
System reset input pin (0 active)
0: System reset 1: Normal operation
79
RESET
I
Apply ICLK cycle one and more time during “0” level after VDD
voltage has reached the specified level in System reset operation.
5/13
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