FEDL7041-04
OKI Semiconductor
ML7041
SDA, SCL
SDA is the serial data input/output pin and SCL is the serial clock line input pin. A pull-up register of 1 to 10 kΩ is
required for the SDA pin. The master clock is required when data is written or read.
Transfer format
The control register can be controlled according to the I
2
C bus transfer format.
The control register address is 3 bits long and the register data is 8 bits long. The methods of writing and
reading of data are shown below.
SDA
SCL
A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
S
7-bit slave address
“0011010”
R/W
“0”
A
read-back
mode bit
“0”
register
address
register data
A
A
P
slave address write
register address write
register data write
Figure 3 I
2
C Interface Write Timing
SDA
SCL
A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
S
slave
R/W
address
“0”
A
read-back
mode bit
“0”
register
address
A
Sr
slave
R/W
address “1”
register data
A
register data read
A
P
slave address write
register address write
2
slave address write
Figure 4 I C Interface Read Timing: normal mode
SDA
SCL
A2 A1 A0
B7 B6
B1 B0
B7 B6
B1 B0
S
slave
R/W
address “0”
A
slave address write
read-back
mode bit
“1”
register
address
register data
register data
A
A
register data write
A
register data read
P
register address write
Figure 5 I
2
C Interface Read Timing: read-back mode
ML7041 Slave address “0011010”
S START condition
P STOP condition
Sr Repeated START condition
A
Acknowledged (ML7041 drive SDA to “0”)
A
Not Acknowledged
Don’t care (“0” or “1”)
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