FEDL7041-04
OKI Semiconductor
ML7041
SG
Analog signal ground.
The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors 0.1 µF ceramic type between this
pin and GND to get the specified noise characteristics. During power-down, this output voltage is 0 V.
SWA, SWB, SWC
Used for an internal analog switch. The pin SWB is connected to the pin SWA or the pin SWC. This is controlled
by CR1-B1.
RG1PDN, RG1IN, RG1O
Used for Regulator 1. The RG1PDN pin is a power down input. When set to “L”, the Regulator 1 changes to the
power down state. Since the power down is controlled by a logical OR with CR5-B4 of the control register, set
CR5-B4 to logic “0” when using this pin. The RG1IN pin is input to the Regulator 1. The RG1O pin is output from
the Regulator 1, whose voltage is 3.0 V. A 1
µF
ceramic type bypass capacitor must be connected between the
power input pin and GND, and a 10
µF
tantalum bypass capacitor must be connected from the output pin to GND.
RG2PDN, RG2IN, RG2O
Used for Regulator 2. The RG2PDN pin is a power down input. When set to “L”, the Regulator 2 changes to the
power down state. Since the power down is controlled by a logical OR with CR5-B5 of the control register, set
CR5-B5 to logic “0” when using this pin. The RG2IN pin is the input to the Regulator 2. The RG2O pin is the
output from the Regulator 2, whose voltage is 3.0 V. A 1
µF
ceramic type bypass capacitor must be connected
between the power input pin and GND, and a 10
µF
tantalum bypass capacitor must be connected from the output
pin to GND.
Note1: The RG1O and RG2O outputs must not be used as the 3 V supply for the ML7041.
Note2: The RG1IN and RG2IN should be common near the device and supplied from the same power supply.
GP1, GP2, GP3, GP4
General purpose driver output. Each pin is controlled by CR5-B1 through CR5-B4. By selecting CR5-B7, the GP1
pin can be controlled by the receive side sign bit.
V
DD
, V
A
, V
A1
, V
A2
, V
A3
VDD is the digital power supply. VA, VA1, VA2, and VA3 are the analog power supply pins. Since these pins are
separated in the device, connect them as close as possible on the PCB.
DG, AG, AG1, AG2, AG3, AGR1, AGR2, AGGP1, AGGP2
Ground. DG is the digital ground. AG, AG1, AG2, AG3, AGR1, AGR2, AGGP1 and AGGP2 are the analog
ground. Since these pins are separated in the device, connect them as close as possible on the PCB.
PDN
Power down and reset control input.
When set to digital “L”, the device changes to the power down state and the control register is reset. Since the
power down mode is controlled by a logical OR with CR0-B5 of the control register, set CR0-B5 to logic “0” when
using this pin. The reset pulse width must be 200 ns or more. Be sure to reset the control register after turning on
the power.
MCK
Master clock input.
The frequency must be 2.048 MHz. MCK can be asynchronous with SYNC and BCLK.
If a frequency of BCLK is 2.048 MHz, the BCLK can be shared with MCK.
BCLK
Shift clock input for the PCM data.
The frequency is set in the range of 64 kHz to 2048 kHz for A/µ-law PCM data and set in the range of 128 kHz to
2048 kHz for linear code selection.
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