Preliminary
ML696201 and ML69Q6203
Functional Description
• CPU
• DMA controller
- Four channels
- 32-bit RISC CPU (ARM946E)
- Built-in 8-KB instruction cache and 8-KB data cache
- Little-endian format
- Maximum operating frequency of 120 MHz
- Instruction structure – Highly dense 32-bit long instructions and their
subset 16-bit long instructions with high object code efficiency can be
executed by switching between them.
- Fixed mode or round-robin mode priority can be selected
- The cycle-steal mode or burst-mode bus access privilege can be selected
- Software requests and external requests are supported as DMA transfer
requests
- A maskable interrupt request is issued to the CPU for each channel after
the specified number of DMA transfers is complete or after an error
occurs
- 31 General-purpose registers x 32 bits
- Maximum transfer count is 65,536 (64K)
- Data transfer sizes are 8, 16, or 32 bits
- Built-in barrel shifter – The operations of the ALU and barrel shift can be
executed by one instruction.
- Built-in multiplier (32 bits x 16 bits)
- Built-in debug function (JTAG)
• High speed USB Port
- USB Protocol 2.0 compliant
• Cache memory
- Connectable to USB 1.1
- 8-KB Instruction and 8 KB Data cache memory
- 4-Way set associative, 1 line, 16 bytes
- Connectable to High Speed (480 Mbps) or Full Speed (12 Mbps)
- The internal bus is connected to the AHB bus.
- Built in PHY
- Supports six programmable endpoints.
- Supports 4-KB multi-configurable FIFO memory
• Internal memory
- Built-in 128-KB SRAM (32 KWords x 32 bits)
- AHB bus connection
• IDE Controller
- Built-in 16-KB ROM for boot up (4 KWords x 32 bits)
- Maximum frequency is 60 MHz
- DMA and Ultra DMA are supported.
- Switchable to NAND Flash + GPIO using the IDEMODE pin
• Flash
- ML69Q6203: (256-K x 16-bit) Flash ROM is embedded in the MCP
(Multi-chip Package)
• PWM
- ML696201: Version without Flash ROM
- PWM x 1 channel (16-bit resolution)
• Watchdog timer
• µPLAT external memory controller (16-bit devices)
- ROM (Flash) access function
Supports 16- bit devices.
- 16-bit timer
Supports asynchronous type Rooms.
Supports FLASH memories.
In models equipped with MCP Flash, the access to Flash is controlled.
- SRAM access function
Supports 16- bit devices
Supports asynchronous type SRAMs
Allows setting of access timing
- SDRAM access function – supports distributed CBR
Supports 16- bit devices
Supports distributed CBR
Allows setting of access timing
- External I/O access function
- Interval-mode or watchdog-mode can be selected
- An interrupt or a reset can be generated
- Cycles can be set to 8.7, 35.0, 140.0 or 559.2 ms
• Analog-to-digital converter
- 10-bit successive approximation type x 4 channels
- Sample / hold function
- Shortest conversion time is 6.7 µs
2
• I C Bus Controller
2
- I C bus single-channel master-mode compliant controller
- Communication speed is 100/400 kbps
- Supports 7-bit and 10-bit addressing
- Communication voltage is 2.7V to 3.3V
two banks of I/O space with two chip select pins for each bank
Supports 16- bit devices
Supports external wait input inputs
Allows setting of access timing for each bank
• Timer
- 16-bit auto reload timer x 3 channels
- A different clock can be set for each channel.
- One-shot mode or interval mode can be set for each channel.
- Cycle can be set from 0.133 µs to 2.237 s
• µPLAT interrupt controller / extended-interrupt controller
- FIQ – One source (external source)
• Synchronous Serial I/O (SSIO)
- 28 IRQ sources (23 internal sources and 5 external sources)
- Eight interrupt priority levels can be set for each interrupt source
- Release of STANDBY mode – A clock stop cancellation request is gener-
ated when the clock is stopped.
- 8-bit clock synchronous serial port x 2 channels
- Maximum transfer rate: 15 Mbps
- 1/1, 1/2, 1/4, 1/16, 1/32 or 1/128 of the frequency of CCLK, or timer
overflow clock can be selected.
- LSB first or MSB first selectable
- Master or slave mode selectable
• µPLAT system timer
- 16-bit auto reload timer x 1 channel
- Cycle is 2.133 µs to 139.5 ms
- Transmit/receive interrupt, transmit/receive buffer empty interrupt
- Rollback test function
• µPLAT-SIO (UART)
- Full-duplex start-stop synchronization method
- Built-in baud-rate generator
• Universal Registers
- Four 8-bit general-purpose internal status/setup registers
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