ML675001/ML67Q5002/ML67Q5003
List of Pins (Continued)
Pin
Primary Function
Secondary Function
LQFP
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
BGA
M4
N5
K5
Symbol
XA[13]
I/O
O
Description
Symbol
I/O
Description
External address output
XA[14]
GND
O
External address output
GND
O
GND
–
–
–
–
–
–
–
O
–
O
O
O
–
O
O
–
–
–
–
–
–
–
–
–
–
–
–
O
O
I
M5
N6
M6
K6
XA[15]
XA[16]
XA[17]
GND
External address output
–
O
External address output
–
O
External address output
–
GND
O
GND
–
L6
XA[18]
PIOC[2]
VDD_IO
PIOC[3]
PIOC[4]
PIOC[5]
VDD_CORE
PIOC[6]
PIOC[7]
XOE_N
VDD_IO
External address output
–
M7
K7
I/O
VDD
I/O
I/O
I/O
VDD
I/O
I/O
O
General port (with interrupt function)
I/O power supply
XA[19]
External address output
–
L7
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
CORE power supply
XA[20]
External address output
External address output
External address output
N7
L8
XA[21]
XA[22]
K8
–
M8
M9
N8
K9
General port (with interrupt function)
General port (with interrupt function)
Output enable (excluding SDRAM)
I/O power supply
XA[23]
External address output
XWR
Transfer direction of external bus
–
VDD
O
–
M10 XWE_N
Write enable
–
N9
L9
XBWE_N[0]
XBWE_N[1]
O
Write enable (LSB)
–
O
Write enable (MSB)
–
L10 XROMCS_N
N10 XRAMCS_N
M11 XIOCS_N[0]
K10 GND
O
External ROM chip select
External RAM chip select
IO chip select 0
–
O
–
O
–
GND
O
GND
–
N11 XIOCS_N[1]
M12 XIOCS_N[2]
N12 XIOCS_N[3]
N13 PIOD[6]
M13 PIOD[7]
L11 PIOB[0]
L13 PIOB[1]
K11 VDD_IO
L12 PIOB[2]
K13 PIOB[3]
J11 PIOB[4]
IO chip select 1
–
O
IO chip select 2
–
O
IO chip select 3
–
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
GND
O
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
I/O power supply
XDQM[1]/XCAS_N[1]
INPUT/OUTPUT mask/CAS (MSB)
INPUT/OUTPUT mask/CAS (LSB)
DMA request signal (CH0)
XDQM[0]/XCAS_N[0]
DREQ[0]
DREQCLR[0]
–
O
–
I
DREQ Clear Signal (CH0)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
GND
DREQ[1]
DREQCLR[1]
TCOUT[0]
TCOUT[1]
PWMOUT[0]
PWMOUT[1]
–
DMA request signal (CH1)
DREQ Clear Signal (CH1)
DMAC Terminal Count (CH0)
DMAC Terminal Count (CH1)
PWM output (CH0)
O
O
O
O
O
–
–
–
–
I
K12 PIOB[5]
J13 PIOC[0]
J10 PIOC[1]
J12 GND
PWM output (CH1)
H13 XBS_N[0]
H12 XBS_N[1]
H10 VDD_CORE
H11 PIOD[0]
G12 PIOD[1]
External bus byte select (LSB)
External bus byte select (MSB)
CORE power supply
–
O
–
VDD
I/O
I/O
–
General port (with interrupt function)
General port (with interrupt function)
XWAIT
XCAS_N
Wait input signal for I/O Banks 0, 1
Column address strobe (SDRAM)
O
April 2004, Rev 2.0
Oki Semiconductor • 9
OKI [ OKI ELECTRONIC COMPONETS ]
