ML675001/ML67Q5002/ML67Q5003
Pin Configuration
PIOD[6]/ XIOCS_N XIOCS_N XRAMCS XBWE
XDQM[1] [3] [1] _N _N[0]
PIOC[4]/
XA[21]
N
M
L
XOE_N
XA[16]
XA[17]
XA[14]
XA[15]
XA[11]
XA[13]
XA[9]
XA[7]
XA[4]
XA[6]
XA[5]
PIOD[7]/ XIOCS_N XIOCS_N XWE_N PIOC[7]/ PIOC[6]/ PIOC[2]/
XA[10]
XDQM[0]
[2]
[0]
XWR
XA[23]
XA[19]
PIOB[1]/
DREQCL
R[0]
PIOB[2]/ PIOB[0]/ XROMCS XBWE_N PIOC[5]/ PIOC[3]/
XA[18]
GND
XA[12]
GND
VDD_IO
XA[3]
XA[8]
XA[0]
XA[2]
GND
DREQ[1] DREQ[0]
_N
[1]
XA[22]
XA[20]
PIOB[3]/ PIOB[5]/
DREQCLR[ TCOUT
VDD_IO
GND
VDD_IO
VDD_
CORE
VDD_IO
XD[13]
XA[1]
K
J
1]
[1]
PIOC[0]/
PWMOUT[
0]
PIOB[4]/ PIOC[1]/
TCOUT PWMOUT
GND
VDD_IO
XD[15]
XD[10]
XD[8]
XD[11]
NC
XD[14]
XD[12]
XD[9]
XD[5]
XD[4]
XD[1]
[0]
[1]
XBS_N
[0]
XBS_N PIOD[0]/
[1] XWAIT
VDD_
CORE
VDD_
CORE
H
G
F
PIOD[2]/ PIOD[1]/ VDD_IO
XRAS_N XCAS_N
GND
VDD_IO
GND
CLKMD1
XD[6]
144-Pin LFBGA
(TOP VIEW)
BSEL[1] PIOD[5]/ PIOD[3]/ PIOD[4]/
XSDCKE XSDCLK XSDCS_N
XD[7]
PIOE[7]/ BSEL[0] PIOE[8]/ PIOE[5]/
GND
XD[2]
CLKMD0
XD[3]
E
EXINT[2]
EXINT[3] EXINT[0]
PIOE[0]/ PIOE[6]/ PIOE[9]/ PIOE[2]/ OSC1_N PIOA[1]/
AIN[0]
AIN[1]
VREFP
VREFN
AIN[3]
AGND
VDD_IO
GND
VDD_IO
FWR
D
C
B
A
SCLK
EXINT[1] EFIQ_N
SDO
SOUT
TDI
PIOE[1]/
SDI
CKO
TCK
TMS
CKOE_N
AVDD
VDD_
CORE
PIOA[5]/
DTR
XD[0]
RESET
_N
nTRST
TDO
GND
VDD_IO PIOA[0/
SIN
GND
PIOA[3]/ PIOA[7]/ PIOE[4]/ PIOB[7]/
DSR
RI
SCL
SRXD
PLLVDD PLLGND
JSEL
11
DRAME_
N
OSC0
9
TEST
8
AIN[2]
7
PIOA[2]/ PIOA[4]/ PIOA[6] PIOE[3]/ PIOB[6]/
CTS
TEST1
DCD
RTS
SDA
STXD
13
12
10
6
5
4
3
2
1
Figure 1. 144-Pin LFBGA
Notes:
1. For pins that have multiple functions, the signals are noted by their pri-
mary / secondary functions.
2. NC pins are electrically unconnected in the package. NC pins can be
connected to VDD or GND.
6 • Oki Semiconductor
April 2004, Rev 2.0
OKI [ OKI ELECTRONIC COMPONETS ]
