FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin
LQFP BGA
Primary Function
Description
Secondary Function
Symbol
I/O
I/O
Symbol
I/O
Description
79
80
81
K13 PIOB[3]
J11 PIOB[4]
K12 PIOB[5]
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
DREQCLR[1]
O
DREQ Clear Signal
(CH1)
I/O
I/O
TCOUT[0]
TCOUT[1]
O
O
DMAC Terminal Count
(CH0)
DMAC Terminal Count
(CH1)
82
83
84
85
86
87
88
J13
J10
J12
PIOC[0]
PIOC[1]
GND
I/O
I/O
General port (with interrupt function)
General port (with interrupt function)
PWMOUT[0]
O
O
—
—
—
—
I
PWM output (CH0)
PWM output (CH1)
PWMOUT[1]
GND GND
—
H13 XBS_N[0]
H12 XBS_N[1]
H10 VDD_CORE
H11 PIOD[0]
O
O
External bus byte select (LSB)
External bus byte select (MSB)
—
—
VDD CORE power supply
—
I/O
General port (with interrupt function)
XWAIT
Wait input signal for I/O
Banks
89
G12 PIOD[1]
I/O
General port (with interrupt function)
XCAS_N
O
Column address strobe
(SDRAM)
90
91
92
G10 GND
GND GND
—
—
—
O
G11 VDD_IO
G13 PIOD[2]
VDD I/O power supply
—
I/O
General port (with interrupt function)
XRAS_N
Row address strobe
(SDRAM/EDO-DRAM)
93
94
F11
F10
F12
PIOD[3]
PIOD[4]
PIOD[5]
I/O
I/O
I/O
I
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
Select boot device
XSDCLK
XSDCS_N
XSDCKE
—
O
O
O
—
—
I
Clock for SDRAM
Chip select for SDRAM
Clock enable (SDRAM)
95
96
E12 BSEL[0]
F13 BSEL[1]
97
I
Select boot device
—
98
E10 PIOE[5]
D12 PIOE[6]
E13 PIOE[7]
E11 PIOE[8]
D11 PIOE[9]
D13 PIOE[0]
C12 PIOE[1]
D10 PIOE[2]
C13 TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
General port (with interrupt function)
JTAG Data Input
EXINT[0]
EXINT[1]
EXINT[2]
EXINT[3]
EFIQ_N
SCLK
SDI
Interrupt input
Interrupt input
Interrupt input
Interrupt input
FIQ input
99
I
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
I
I
I
I/O
I
SSIO clock
SSIO Serial Data In
SSIO Serial Data Out
SDO
—
O
—
—
—
—
—
—
—
—
—
—
B12 TDO
O
JTAG data out
—
B13 nTRST
A13 PLLVDD
A12 PLLGND
C11 CKO
I
JTAG reset
—
VDD Power supply for PLL
GND GND for PLL
—
—
O
I
Clock output
JTAG select
—
A11 JSEL
—
C10 TMS
I
JTAG mode select
JTAG clock
—
B11 TCK
I
—
A10 DRAME_N
I
DRAM enable
—
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