FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Primary /
Pin Name
I/O
Description
Logic
Secondary
External Bus
XA[23:19]
O
Address bus to external RAM, external ROM, external I/O banks, and
external DRAM. After a reset, these pins are configured for their primary
function (PIOC[6:2]).
Secondary
Positive
XA[18:0]
XD[15:0]
O
Address bus to external RAM, external ROM, external I/O banks, and
external DRAM.
—
—
Positive
Positive
I/O
Data bus to external RAM, external ROM, external I/O banks, and external
DRAM.
External bus control signals (ROM/SRAM/IO)
XROMCS_N
XRAMCS_N
XIOCS_N[0]
XIOCS_N[1]
XIOCS_N[2]
XIOCS_N[3]
XOE_N
O
O
O
O
O
O
O
O
O
ROM bank chip select
SRAM bank chip select
IO chip select 0
—
—
—
—
—
—
—
—
—
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
IO chip select 1
IO chip select 2
IO chip select 3
Output enable/ Read enable
Write enable
XWE_N
XBS_N[1:0]
Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB
XBWE_N[0]
XBWE_N[1]
XWR
O
O
O
LSB Write enable
MSB Write enable
—
—
Negative
Negative
—
Data transfer direction for external bus, used when connecting to Motorola
I/O devices. This represent the secondary function of pin PIOC[7].
Secondary
L: read , H: write. Available for I/O bank 0/1.
External I/O bank 0/1/2/3 WAIT signal.
XWAIT
I
Secondary
Positive
This input permits access to devices slower than register settings.
External bus control signals (DRAM)
XRAS_N
O
O
O
O
O
O
Row address strobe. Used for both EDO DRAM and SDRAM
Column address strobe signal (SDRAM)
SDRAM clock (same frequency as internal HCLK)
Clock enable (SDRAM)
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Negative
Negative
—
XCAS_N
XSDCLK
XSDCKE
—
XSDCS_N
XDQM[1]/XCAS_N[1]
Chip select (SDRAM)
Negative
Positive/
Negative
Positive/
Negative
Connected to SDRAM: DQM (MSB)
Connected to EDO DRAM: column address strobe signal (MSB)
Connected to SDRAM: DQM (LSB)
XDQM[0]/XCAS_N[0]
O
Secondary
Connected to EDO DRAM: column address strobe signal (LSB)
11/24
OKI [ OKI ELECTRONIC COMPONETS ]
