FEDL671000-02
1
Semiconductor
ML671000
BLOCK DIAGRAM
nRST
nEA
DBSEL
TEST
TMS
nTRST
TDI
TCK
TDO
ARM7DTMI
RAM
P0[7:0]/XA[23:16]
XA[15:1]
XA0/nLB
XD[15:0]
nR/W
nCS0
nRD
nWRE/nWRL
P1.7/nXWAIT
P1.6/nCS1
P1.5/nHB/nWRH
P1.4/nRAS1
P1.3/nWH/nCASH
P1.2/nRAS0
P1.1/nCAS/nCASL
P1.0/nWL/nWE
P6.7/nBACK
P6.6/nBREQ
V
DD
V
SS
32-bit Core Address Bus
32-bit Core Address Bus
Internal Bus/External Memory Controller
P6.5/DACK1
P6.4/DACK0
P6.3/nDREQ1
P6.2/nDREQ0
P5.7/ DTR
P5.6/ RTS
P5.5/ CTS
P5.4/ DSR
P5.3/ DCD
P5.2/ RI
P5.1/OUT1
P5.0/OUT2
P4.7/SOUT
P4.6/ SIN
P4.5/TXD0
P4.4/RXD0
P4.3/ TXC
P4.2/ RXC
nEFIQ
2-channel
DMAC
Interrupt
Controller
P2[7:0]/nEIR[7:0]
UART Port
Bus (16 bits)
Time Base
Generator
Peripheral Address Bus
Serial Port
Peripheral Address
Flexible Timer/
Auto-reload Timer
(two each)
P3.7/TMCLK3
P3.6/TMCLK2
P3.5/TMCLK1
P3.4/TMCLK0
P3.3/TMIN1/TMOUT1
P3.2/TMIN0/TMOUT0
USB Device Controller
D+
D
−
I/O Port
PLL
OSC0
OSC1
CLKOUT
PLLEN
OSCV
DD
OSCV
SS
P7[7:0]
P6[7:0]*
P4[7:0]*
P3[7:0]*
P2[7:0]*
P1[7:0]*
P5[7:0]*
P0[7:0]*
Asterisks indicate pins with secondary functions.
3/25
OKI [ OKI ELECTRONIC COMPONETS ]
