FEDL63193-04
1Semiconductor
ML63193
PAD CONFIGURATION
Pad Layout
64 COM16
63 COM15
62 COM14
61 COM13
60 COM12
59 COM11
58 COM10
57 COM9
56 SEG63
55 SEG62
54 SEG61
53 SEG60
52 SEG59
51 SEG58
50 SEG57
49 SEG56
48 SEG55
47 SEG54
46 SEG53
45 SEG52
44 SEG51
43 SEG50
42 SEG49
41 SEG48
40 SEG47
39 SEG46
38 SEG45
37 SEG44
36 SEG43
35 SEG42
34 SEG41
33 SEG40
PB.0 96
PB.1 97
PB.2 98
PB.3 99
PA.0 100
PA.1 101
PA.2 102
PA.3 103
P9.0 104
P9.1 105
P9.2 106
P9.3 107
P0.0 108
P0.1 109
P0.2 110
ML63193
Y
X
P0.3 111
(0,0)
VSS 112
COM1 113
COM2 114
COM3 115
COM4 116
COM5 117
COM6 118
COM7 119
COM8 120
SEG0 121
SEG1 122
SEG2 123
SEG3 124
SEG4 125
SEG5 126
SEG6 127
SEG7 128
Chip size
: 5.72 mm × 5.72 mm
Chip thickness
Coordinate origin
Pad hole size
Pad size
: 350 µm (280 µm: available as required)
: center of chip
: 100 µm × 100 µm
: 110 µm × 110 µm
Minimum pad pitch : 140 µm
Note: The chip substrate voltage is VSS.
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