ML2650 DATASHEET (Digest)
Pin Description
Pin
No.
Pin Name
Buffer
Type
Power
Description
Reset
or
Sleep
state
-
-
F1
A6
SYSCLK
RESETB
Input
Schmitt Input
w ith Delay
IOVDD
IOVDD
System clock input.
Hardware reset pin. When the pin is “L”, LSI is in reset
status.
D2
D1
C2
C1
C3
B2
B3
A1
C4
A3
A4
A5
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RDB
WRB
ILE
4mA I/O
4mA I/O
4mA I/O
4mA I/O
4mA I/O
4mA I/O
4mA I/O
4mA I/O
Schmitt Input
Input
Schmitt Input
Input
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
Data input/output pin.
Data input/output pin.
Data input/output pin.
Data input/output pin.
Data input/output pin.
Data input/output pin.
Data input/output pin.
Data input/output pin.
Chip select pin.
Read enable pin.
Write enable pin.
When ILE pin is “H”, D7-0 is used for index. When it’s
“L”, data from D7-0 is used for data.
Interrupt output pin. It outputs “H” level, when the
interrupt is generated.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
D4
IRQ
4mA Output
IOVDD
Low
D3
LRCLK
4mA I/O
IOVDD
LR clock input/output for SAI. Please pulldown to
DGND because this pin is input mode in slave.
Bit clock input/output for SAI. Please pulldown to
DGND because this pin is input mode in slave.
Serial data input for SAI. Please input data from left
channel first. Please pulldown to DGND when SAI
not use.
256fs clock input in slave mode.
In master mode, controllable 256fs clock output.
Please pulldown to DGND because this pin is input
mode in slave.
Headphone output left.
Hi-Z
F4
BCLK
4mA I/O
IOVDD
Hi-Z
F3
SAIIN
Input
IOVDD
Hi-Z
F2
MCLK
4mA I/O
IOVDD
Hi-Z
D5
HPOUTL
Tristate Output
HPLVDD
Hi-Z
Version 1.1
7 / 20
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