ML2650 DATASHEET (Digest)
Application Example
ML2650
HPOUTL
HPOUTR
D7-D0
CSB
WRB
RDB
ILE
Refer to application
example circuit below
HPLVDD
HPRVDD
HPLGND
HPRGND
CPU
DSP
IRQ
LRCLK
BCLK
SAIIN
IOVDD
IOVDD
MCLK
DVDD
DVDD
0.1uF
0.1uF
This C,R parameter
applies for 32.768kHz
SYSCLK input.
RESETB
SYSCLK
DGND
DGND
0.1uF
0.1uF
PLLC
220Ω
150nF (B or
X7R spec)
TMODE1
TMODE0
PLLVDD
PLLGND
1500nF
0.1uF
(B or X7R spec)
Liner
Regulator
100uF
HPLVDD
HPRVDD
100uH
220uF
HPOUTL
0.1uF
0.1uF
0.1uF
HPLGND
HPRGND
100uH
220uF
HPOUTR
0.1uF
Note. Capacitance tolerance is permitted within 10%, resistance tolerance is permitted within 5%, if no special mention.
Version 1.1
5 / 20