FEDL2110-01
OKI Semiconductor
ML2110
DRAM Access
(V
DD
= 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
RAS
Delay Time
RAS
Pulse Width
A to
RAS
Time
CAS
Delay Time
CAS
Pulse Width
A to
CAS
Time
RAS
to
CAS
Time
WE
to
CAS
Time
WE
Delay Time
WE
Pulse Width
A to
WE
Time
Required
Precharge Time
CAS
to
RAS
Time
CAS
to D Time
Symbol
t
RAS
t
W_RAS
t
W_ARAS
t
CAS
t
W_CAS
t
W_ACAS
t
W_RASCAS
t
W_WECAS
t
WE
t
W_WE
t
W_AWE
t
W_PREC
t
W_CASRAS
t
W_EDO
Condition
—
—
—
2nt access falling
edge
Normal
Normal
Refresh
—
—
—
—
—
—
—
—
Hyper Mode
Min.
—
3
1
—
—
1.5
4
0.5
1.5
1.5
—
3
—
1
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
1
—
1
—
Max.
24
Note 1
—
22+0.5t
CYC
22
2
5
1
2
2
23
Note 1
—
Note 2
—
1
Unit
ns
t
CYC
t
CYC
ns
ns
t
CYC
t
CYC
ns
t
CYC
t
CYC
ns
t
CYC
t
CYC
t
CYC
t
CYC
t
CYC
General Device Access
(V
DD
= 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
AS
Delay Time
Symbol
t
AS
Condition
—
Min.
—
Typ.
—
Max.
27
Unit
ns
9/101
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