FEDL2110-01
OKI Semiconductor
ML2110
Symbol
CLK
XO
CLKA
CLKB
CLKENA
CLKFDBL
RST
STBY
EXTINT1-0
WAIT
BR3
BGT3
MD
TSTM2-0
I/O
I
O
O
O
I
I
I
I
I
I/O
I
O
I
I
Clock input signal.
Clock signal. Inverse of CLK.
Internal clock signal.
Description
Internal clock signal. Inverse of CLK.
Clock change signal.
Clock cycle change signal.
Reset input.
Standby signal.
STBY
suspends operation and places ML2110 in a standby
state.
External interrupt signal.
Wait signal. Normally, it is pulled up ‘H’ level.
Cache/BIU test signal.
Cache/BIU test signal.
16/32 bit select signal.
Test mode select input signal.
5/101