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MK31VT864A-8YC 参数 Datasheet PDF下载

MK31VT864A-8YC图片预览
型号: MK31VT864A-8YC
PDF下载: 下载PDF文件 查看货源
内容描述: 8,388,608字×64位同步动态RAM模块( 1BANK ) [8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK)]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 11 页 / 106 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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MK31VT864A-8YC 98.07.17  
AC CHARACTERISTIC  
(
)
Vcc=3.3V ± 0.3V, Ta = 0 to 70 °C  
NOTE 1, 2  
.
Module Spec.  
Unit Note  
Parameter  
Symbol  
Min.  
Max.  
Clock Cycle Time  
CL=3  
8
12  
-
-
ns  
ns  
t
CC  
CL=2  
CL=3  
CL=2  
-
Access Time from Clock  
6
ns  
3, 4  
3, 4  
t
AC  
-
10  
ns  
Clock "H" Pulse Time  
Clock "L" Pulse Time  
Input Setup Time  
Input Hold Time  
3
-
ns  
t
CH  
3
-
ns  
t
CL  
2
-
ns  
t
SI  
HI  
1
-
ns  
t
Output Low Impedance Time from Clock  
Output High Impedance Time from Clock  
Output Hold from Clock  
3
-
ns  
t
OLZ  
OHZ  
-
8
ns  
t
3
-
ns  
3
t
OH  
/RAS Cycle Time  
80  
30  
48  
20  
8
-
ns  
t
RC  
/RAS Precharge Time  
-
ns  
t
RP  
/RAS Active Time  
100,000  
ns  
t
RAS  
RCD  
/RAS to /CAS Delay Time  
Write Recovery Time  
-
-
ns  
t
ns  
t
WR  
/RAS to /RAS Bank Active Delay Time  
Refresh Time  
16  
-
-
ns  
t
RRD  
64  
-
ms  
ns  
t
REF  
PDE  
Power-down Exit Set-up Time  
Input Level Transition Time  
/CAS to /CAS Delay Time (Min)  
Clock Disable Time from CKE  
Data Output High Impedance Time from  
t
t +1CLK  
SI  
-
3
ns  
t
T
1
1
2
Cycle  
Cycle  
Cycle  
I
CCD  
I
CKE  
I
DOZ  
DQMB  
Data Input Mask Time from DQMB  
0
0
3
2
2
2
Cycle  
Cycle  
Cycle  
Cycle  
Cycle  
Cycle  
I
DOD  
Data Input Time from Write Command  
I
DWD  
Data Output High Inpedance  
CL=3  
CL=2  
I
ROH  
Time from Precharge Command  
Active Command Input Time from MODE  
Write Command Input Time from Output  
I
MRD  
t
OWD  
NOTES:  
1) AC measurements assume tT=1ns.  
2) The reference level for timing of input signals is 1.4V.  
3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF  
(RLoad is 50ohm).  
4) An access time is measured at 1.4V.  
5) If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL.  
50Ω  
OUTPUT LOAD  
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