s
MG63P/64P/65P
s
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Figure 8
shows an array base after placement of the optimized memory macrocells.
High-density SRAM
Mega macrocells
Embedded SDRAM
Figure 8. Optimized Memory Macrocell Floor Plan
3. Place and route logic into the array transistors.
- Oki Design Center engineers use layout software and customer performance specifications
to connect the random logic and optimized memory macrocells.
Figure 9
marks the area in which placement and routing is performed with cross hatching.
Figure 9. Random Logic Place and Route
Figure 10
illustrates Oki’s Embedded DRAM ASIC. Oki provides two types of reconfigurable SDRAM
cores generated from the compiler.
4
Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
