PEDD56V62320K-01
OKI Semiconductor
MD56V62320K
PIN DESCRIPTION
CLK
Fetches all inputs at the “H” edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
UDQM and LDQM.
CS
Masks system clock to deactivate the subsequent CLK operation.
CKE
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Address
BA0, BA1
Row address
Column Address
: RA0 – RA10
: CA0 – CA7
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of the
clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H”
edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte.
DQM0 - 3
DQ1 - 32
Data inputs/outputs are multiplexed on the same pin.
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