¡ Semiconductor
MD51V64405
Notes: 1. Astart-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t = 2 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
The output timing reference levels are V = 2.0 V and V = 0.8 V.
OH
OL
5. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAC
is greater than the specified
RCD
t
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
RCD
RCD
RCD
.
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified
RAD
RAC
t
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
RAD
RAD
RAD
.
AA
7. t
(Max.), t
(Max.), t
(Max.) and t
(Max.) define the time at which the
OEZ
CEZ
REZ
WEZ
outputachievestheopencircuitconditionandarenotreferencedtooutputvoltage
levels.
8. t
9. t
and t
must be satisfied for open circuit condition.
REZ
CEZ
or t
must be satisfied for a read cycle.
RRH
RCH
10. t
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance)throughouttheentirecycle. Ift ≥t (Min.), t ≥t (Min.),
CWD CWD
RWD RWD
t
≥t
(Min.) and t
≥t
(Min.), then the cycle is a read modify write
AWD AWD
CPWD CPWD
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
8/15
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