FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
ABSOLUTE MAXIMUM RATINGS
Parameter
Analog power supply
voltage
Symbol
AVDD
Condition
—
Rating
Unit
V
–0.3 to +4.6
Digital power supply
voltage
Analog input voltage
DVDD
—
–0.3 to +4.6
V
VAIN
VDIN1
Analog pin
Normal digital pin
–0.3 to AVDD+0.3
–0.3 to DVDD+0.3
–0.3 to +6.0
–0.3 to DVDD+0.3
–20 to +20
V
V
V
Digital input voltage
DVDD = 3.0 to 3.6 V
DVDD < 3.0 V
—
VDIN2
5 V tolerant pin
V
Output current
Power dissipation
Storage temperature
IO
PD
Tstg
mA
mW
°C
Ta = 60 °C, per package
350
–65 to +150
—
RECOMMENDED OPERATING CONDITIONS
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Parameter
Symbol
AVDD
DVDD
Ta
Condition
Min.
3.0
3.0
Typ.
3.3
3.3
—
Max.
3.6
3.6
Unit
V
V
Analog power supply voltage
Digital power supply voltage
Operating temperature range
—
—
—
–20
60
°C
0.75 ×
DVDD
0.75 ×
DVDD
DVDD+
0.3
VIH1
VIH2
VIL
Normal digital pin
5 V tolerant pin
Digital pin
—
—
—
V
V
V
Digital high-level input voltage
5.5
0.19 ×
DVDD
20
Digital low-level input voltage
–0.3
Digital input rise time
Digital input fall time
tIR
tIF
Digital pin
Digital pin
—
—
2
2
ns
ns
20
Digital output load capacitance
Digital output load resistance
AVREF bypass capacitor
VREGOUT bypass capacitor
VBG bypass capacitor
Master clock frequency
PCM shift clock frequency
PCM synchronous signal
frequency
CDL
RDL
Cvref
Cvout
CVBG
Fmck
Fbclk
Digital pin
—
—
—
—
10+0.1
150
50
—
4.7+0.1
—
pF
Pull-up resistance, PCMO
Between AVREF-AGND
Between VREGOUT-DGND
Between VBG-DGND
MCK
500
2.2+0.1
—
Ω
µF
µF
pF
MHz
kHz
—
—
–0.01% 12.288 +0.01%
BCLK (at input)
64
—
2048
Fsync
SYNC (at input)
—
8.0
—
kHz
Clock duty ratio
DRCLK
tBS
tSB
MCK, BCLK (at input)
BCLK to SYNC (at input)
SYNC to BCLK (at input)
SYNC (at input)
40
100
100
50
—
—
—
60
—
—
%
ns
ns
µs
PCM synchronous timing
PCM synchronous signal width
tWS
1BCLK
100
(Note) On power-on/shut-down sequence
For the analog power supply voltage (AVDD) and the digital power supply voltage (DVDD) to be supplied to
this LSI, it is recommended that power be applied to them simultaneously. However, if simultaneous power-up
is difficult due to the power supply circuit configuration, power them up in the order of DVDD → AVDD.
The power supplies should be shut down in the reverse order of power-on sequence.
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