¡ Semiconductor
Slave Mode
Symbol
t
AR
t
AW
t
CW
t
DW
t
RA
t
RDE
t
RDF
t
RSTD
t
RSTS
t
RSTW
t
RW
t
WA
t
WC
t
WD
t
WWS
Item
Time from Address Valid or
CS
Leading Edge to
IOR
Leading Edge
Address Valid Set-up Time
to
IOW
Trailing Edge
CS
Leading Edge Set-up Time
to
IOW
trailing edge
Data Valid Set-up Time
to
IOW
Trailing Edge
Address or
CS
Hold Time
to
IOR
Trailing Edge
Data Access Time
to
IOR
Leading Edge
Delay Time to Data Floating Status
from
IOR
Trailing Edge
Supply Power Leading Edge Set-up
time to RESET Trailing Edge
Time to First Active
IOR
or
IOW
from RESET Trailing Edge
RESET Pulse Width
IOR
Pulse Width
Address Hold Time
to
IOW
Trailing Edge
CS
Trailing Edge Hold Time
to
IOW
Trailing Edge
Data Hold Time to
IOW
Trailing Edge
IOW
Pulse Width
Min.
50
130
130
130
0
—
0
500
2t
CY
300
200
20
20
30
160
MSM82C37B-5RS/GS/VJS
(Ta = –40 to +85°C, V
CC
= 4.5 to 5.5 V)
Comments
Max.
Unit
—
—
—
—
—
140
70
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Notes: 1. Output load capacitance of 150 (pF).
2.
IOW
and
MEMW
pulse widths of t
CY
– 100 (ns) for normal writing, and 2t
CY
– 100
(ns) for extended writing.
IOR
and
MEMR
pulse widths of 2t
CY
– 50 (ns) for normal
timing, and t
CY
– 50 (ns) for compressed timing.
3. DREQ and DACK signal active level can be set to either low or high. In the timing
chart, the DREQ signal has been set to active-high, and the DACK signal to active-
low.
4. When the CPU executes continuous read or write in programming mode, the
interval during which the read or write pulse becomes active must be set to at least
400 ns.
5.
EOP
is an open drain output. The value given is obtained when a 2.2 kW pull-up
resistance is connected to V
CC
.
6. Rise time and fall time are less than 10 ns.
7. Waveform measurement points for both input and output signals are 2.2 V for HIGH
and 0.8 V for LOW, unless otherwise noted.
7/33
OKI [ OKI ELECTRONIC COMPONETS ]
