¡ Semiconductor
MSM82C37B-5RS/GS/VJS
AC CHARACTERISTICS
DMA (Master) Mode
Symbol
t
AEL
t
AET
t
AFAB
t
AFC
t
AFDB
t
AHR
t
AHS
t
AHW
Item
Delay Time from CLK Falling Edge
up to AEN Leading Edge
Delay Time from CLK Rising Edge
up to AEN Trailing Edge
Delay Time from CLK Rising Edge
up to Address Floating Status
Delay Time from CLK Rising Edge
up to Read/Write Signal Floating Status
Delay Time from CLK Rising Edge
up to Data Bus Floating Status
Address Valid Hold Time
to Read Signal Trailing Edge
Data Valid Hold Time
to ADSTB Trailing Edge
Address Valid Hold Time
to Write Signal Trailing Edge
Delay Time from CLK Falling Edge
up to Active DACK
t
AK
Delay Time from CLK Rising Edge
up to
EOP
Leading Edge
Delay Time from CLK Rising Edge
up to
EOP
Trailing Edge
t
ASM
t
ASS
t
CH
t
CL
t
CY
Time from CLK Rising Edge
up to Address Valid
Data Set-up Time to ADSTB Trailing Edge
Clock High-level Time
Clock Low-level Time
CLK Cycle Time
Min.
—
—
—
—
—
t
CY
– 100
30
t
CY
– 50
—
—
—
—
100
68
68
200
(Ta = –40 to +85°C, V
CC
= 4.5 to 5.5 V)
Comments
Max.
Unit
200
130
90
120
170
—
—
—
170
170
170
170
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
(Note 3)
(Note 5)
—
—
—
(Note 6)
(Note 6)
—
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