Total Endurance™ Quick Start Guide
Page Architecture
Microchip’s new EEPROM architecture is page based and forces the entire page to
undergo a write cycle even when individual bytes are addressed. This design supports
pseudo byte writes (or multiple bytes of less than a full page) so the new devices can
be used as a replacement for older devices with no code changes required. All writes
to a page now refresh all of the bytes of the page whether the specific bytes are
addressed or not.
With the new page architecture, the entire page is read into latches at the beginning of
the Write command. As data is received, it is loaded into the appropriate latches to
replace the old data. At the end of the Write command, the entire page is written using
the data in the latches. This is essentially a read-modify-write operation on the entire
page.
Because the entire page endures a write cycle during each write operation, endurance
is specified per page.
How does this affect me?
Most applications should not encounter any issues when moving between these two
architectures due to the high endurance of Microchip EEPROM technology.
Microchip recommends that byte writes be minimized, and for the MCU to buffer the
data and performs either a whole page write, or writes as many bytes in one Write com-
mand as possible.
A side benefit of performing a page write vs. a multiple of individual byte writes is a
reduction in average power consumption; also the total system write time is reduced by
doing fewer total writes. AN1028, “Recommended Usage of Microchip I2C™ Serial
EEPROM Devices,” covers a number of examples showing the code efficiencies and
reduction in time taken between writing individual bytes vs. an entire page.
The data below was collected on actual Microchip devices. It shows that the endurance
is very high for Microchip serial EEPROMS and that most users should not have any
endurance concerns.
© 2011 Microchip Technology Inc.
DS51342B-page 5
MICROCHIP [ MICROCHIP ]
