Total Endurance™ Quick Start Guide
Graphic Results
This shows the failure rate over time (or cycles) up to the lifetime (calculated or entered)
of the application. The Enlarge button displays a full-screen version of the graph.
FAILURE RATE OVER TIME
ARCHITECTURE
Microchip employs two different array architectures in its EEPROM devices. The differ-
ence between the two involves what happens during the write cycle when less than a
full page is written. To the end user, this change does not affect communication; it only
affects how endurance is specified.
Byte Architecture
Microchip’s old EEPROM architecture was a byte architecture that allowed the user to
do a true byte write where only the byte(s) being addressed were modified during the
write cycle. The number of bytes being programmed in this architecture could be
anywhere from one single byte to an entire page.
DS51342B-page 4
© 2011 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
