IRFR9214, IRFU9214, SiHFR9214, SiHFU9214
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-
+
-
+
-
RG
+
-
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
Period
D =
P.W.
V
= - 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
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