MP7611
3
8
3-8
Decoder
A0 to A2
8
8
To first latch bank enable
LD1
CS
8
To switches across the first latch
bank for readback enable
RD
LD2
R1
To second latch bank enable
To reset all first latch bank
To reset all second latch bank
R2
Figure 4. Simplified Parallel Logic Port
2•D
16384
)
Output Voltage = 2 • Vr (--1 +
(Vr = +5 V)
Hex Code
Binary Code
10 • (--1 + 0) = --10
O O O O
00000000000000
16382
10 • (--1 +
) = --1.22 mV
1 F F F
2 O O O
2 O O 1
01111111111111
10000000000000
10000000000001
16384
16384
10 • (--1 +
) = 0
16384
16386
16384
10 • (--1 +
) = 1.22 mV
32766
16384
10 • (--1 +
) = 9.99878
3 F F F
11111111111111
Table 2. MP7611
Ideal DAC Output vs. Input Code
Note: See Electrical Characteristics for real system accuracy
Rev. 3.01
9
EXAR [ EXAR CORPORATION ]
