MP7611
Data
Input/Output
Bus
1
0
t
t
DH
DS
1
0
Address
A0-A2
t
t
AH
AS
t
1
0
CH1
Chip Select
CS
don’t care
don’t care
t
CS1
t
LD1W
Load Latch A
LD1
1
0
t
LD1LD2
1
0
Load Latch B
LD2
t
LD2W
+FS
--FS
Analog Output
t
SD
Figure 1. Loading Latch A and Updating Latch B
Notes:
(1) Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable
in the above diagram.
(2) R1 = R2 = 1.
(3) For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).
t
t
AH
AS
1
0
Address
A0-A2
1
0
Chip Select
CS
don’t care
don’t care
t
t
t
CH2
CS2
RD
1
0
Data Readback
RD
t
t
DR
DA
HIGH-Z
HIGH-Z
Digital Output Data
D0 to D113
1
0
Figure 2. Read Back First Latch Bank of One DAC
Notes:
(1) Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable
in the above diagram.
(2) R1 = R2 = 1.
t
R1W
1
0
R1
R2
Reset first latch bank to
1000 . . . . .0000
t
R2W
1
0
Reset second latch bank to 1000 . . . . .0000 and analog
output to zero volt.
Figure 3. Reset Operations
Rev. 3.01
7
EXAR [ EXAR CORPORATION ]
