Technical Information
EiceDRIVER™ 2ED300C17-S
preliminary
1.4 Block diagram 2ED300C17-S
EDFA
E. A
Fault
VCEsat
VCE sat
A
Detection
Gate A
COM A
Dead
time
Pulse
Stage
Pulse
Former
Soft-
shut down
IN A
CA
VA+
VA-
Under-
voltage
Pulse
Memory
Sense A
DOCD
Dead
time
Sense A
RC A
IN B
CB
Fault
Detection
Logic
EDFA
VCEsat
E. B
Fault
Detection
MODE
VCE sat
B
Gate B
COM B
Pulse
Former
Soft-
shut down
Pulse
Stage
RESET
FAULT
Fault-
Memory
VB+
VB-
Under-
voltage
Pulse
Memory
VDD
VDC
Supply
Voltage
Sense B
DOCD
DC/DC
Sense B
RC B
Converter
Control
GND
1.5 Inputs and outputs 2ED300C17-S
IN A; IN B
PWM signal inputs for channel A and channel B
CA; CB
Mode
Inputs for external interlock delay time generation for channel A and B in half bridge mode
Input for operating mode selection. Direct mode GND; half bridge mode +15V
Reset
With reset and operating PWM signals the primary fault memory is reset. Reset has active high logic. A
high signal activates the reset.
Fault
The fault output indicates a fault. The fault output is open collector.
VDC
Supply for the DC-DC SMPS
VDD
Electronic supply
GND
GND is ground and reference point for all primary signals and the supply voltage
E.A; E.B
External fault input. Is used to set the fault memory by an external signal.
Input for the saturation voltage monitoring
VCE sat A; B
Gate A; B
COM A; B
Driver output to the IGBT module gate via an external gate resistor
COM A; B is connected to the auxiliary emitters of the IGBT module
VA+; VA- ; VB+; VB-
Sense
Non-isolated supply voltage for additional use and connection of the buffer capacitors
Control input for the optional di/dt or dv/dt control, setting of the soft shut down or active clamping
RC network for VCE sat reference curve
RC A; RC B
Page 6
www.eupec.com
www.EiceDRIVER.com
EUPEC [ EUPEC GMBH ]
