Et r on Tech
EM6A9325
4M x 32 LPSDRAM
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank,
Row
ADDRESS
Bank(s)
tRP
READ A
NOP
NOP
NOP
COMMAND
NOP
NOP
Precharge
NOP
Activate
CAS# latency=2
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
, DQ's
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK3
Read to Precharge (CAS# Latency = 2, 3)
5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
DIN A
0
DIN A
DIN A
DIN A
3
don't care
DQ0 - DQ3
1
2
The first data element and the write
Extra data is masked.
are registered on the same clock edge.
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
Preliminary
9
Rev 0.4
June 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
