Et r on Tech
EM6A9325
4M x 32 LPSDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
DQ's
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
DINB
NOP
NOP
DOUT A
0
DINB
DINB
2
0
1
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval (Burst Length
4, CAS# Latency = 3)
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
BANKA
ACTIVATE
READ A
COMMAND
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
, DQ's
DIN A
0
DIN A
DIN A
DIN A
3
t
1
2
CK2
: "H" or "L"
Read to Write Interval (Burst Length 4, CAS# Latency = 2)
≥
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
COMMAND
NOP
NOP
NOP
WRITE B
DIN B
NOP
NOP
NOP
CAS# latency=2
DIN B
1
DIN B
DIN B
3
t
, DQ's
0
2
CK2
: "H" or "L"
Read to Write Interval (Burst Length 4, CAS# Latency = 2)
≥
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
Preliminary
8
Rev 0.4
June 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
