EM6A9160
EtronTech
Test Mode field (A8~A7)
•
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 9. Test Mode
A8
0
A7
0
Test Mode
Normal mode
DLL Reset
1
0
X
1
Test mode
(BA0, BA1)
•
Table 10. MRS/EMRS
BA1
RFU
RFU
BA0
0
A11 ~ A0
MRS Cycle
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low onCS, RAS , CAS , and WE .
The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle asCS,RAS ,
CAS , and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to
writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or
matched impedance. Two clock cycles are required to complete the write operation in the extended mode
register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0
is used for EMRS. Refer to the table for specific codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address Field
0
1
RFU must be set to “0”
DS1 RFU must be set to “0” DS0 DLL Extended Mode Register
BA0 Mode
A6 A1
Drive Strength
Full
Comment
A0
0
DLL
0
0
1
1
0
1
MRS
0
1
0
1
Enable
Disable
EMRS
Weak
1
RFU
Reserved For Future
Matched impedance Output driver matches impedance
9
Rev. 1.3
Apr. /2014
ETRON [ ETRON TECHNOLOGY, INC. ]
