EtronTech
EM638325
2Mega x 32 SDRAM
Overview
The EM638325 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured
as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number
of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then
followed by a Read or Write command.
The EM638325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system can choose the most suitable modes to maximize its
performance. These devices are well suited for applications requiring high memory bandwidth.
Block Diagram
Col um n
De coder
2048
X
256
X
32
CELL ARRAY
(BANK #0)
Sense
Ampl ifier
C O N T R O L
SI GN A L
GE N E R A T O R
DLL
C L O C K
B U FF ER
CL K
C K E
Sense
Ampl ifier
C S #
2048
CELL ARRAY
(BANK #1)
X 256 X 32
COMMAND
D EC O D ER
R A S#
C A S#
W E #
M O D E
R E G I ST E R
Col um n
De coder
CO LU MN
C O U N T ER
A 1 0/A P
Col um n
De coder
2048
CELL ARRAY
(BANK #2)
X 256 X 32
A D D R ESS
B U F FER
A 0
A 9
B S 0
B S 1
Sense
Ampl ifier
R E F R E SH
C O U N T ER
Sense
Ampl ifier
D Q
B U F FER
2048
CELL ARRAY
(BANK #3)
X 256 X 32
D Q 0
│
D Q 3 1
Col um n
De coder
D Q M 0~3
Preliminary
2
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
