Et r on Tech
Overview
EM636165
1M x 16 SDRAM
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K x 16 bit DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 512K x 16 bit bank is organized as 2048 rows by 256 columns by 16 bits. Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number
of locations in a programmed sequence.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance
PC applications.
Block Diagram
CLK
CKE
CLOCK
BUFFER
Column Decoder
2048 X 256 X 16
CELL ARRAY
(BANK #0)
CS#
CONTROL
SIGNAL
GENERATOR
RAS#
CAS#
WE#
LDQM
UDQM
COMMAND
DECODER
Sense Amplifier
COLUMN
COUNTER
DQ0
DQs Buffer
DQ15
MODE
REGISTER
A0
ADDRESS
BUFFER
A11
Sense Amplifier
REFRESH
COUNTER
2048 X 256 X 16
CELL ARRAY
(BANK #1)
Column Decoder
Preliminary
2
Rev. 1.8
Nov 2001
ETRON [ ETRON TECHNOLOGY, INC. ]
